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Preliminary Technical Data
GENERAL FEATURES
Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver ADE5166/ADE5169/ADE5566/ADE5569
MICROPROCESSOR FEATURES
8052-based core Single-cycle 4 MIPS 8052 core 8052-compatible instruction set 32.768 kHz external crystal with on-chip PLL Two external interrupt sources External reset pin Low power battery mode Wake-up from I/O, temperature change, alarm, and universal asynchronous receiver/transmitter (UART) LCD driver operation with automatic scrolling Temperature measurement Real-time clock Counter for seconds, minutes, hours, days, months, and years Date counter including leap year compensation Automatic battery switchover for RTC backup Operation down to 2.4 V Ultralow battery supply current: 1.5 A Selectable output frequency: 1 Hz to 16.384 kHz Embedded digital crystal frequency compensation for calibration and temperature variation 2 ppm resolution Integrated LCD driver 108-segment driver for the ADE5566/ADE5569 and 104-segment driver for the ADE5166/ADE5169 2x, 3x, or 4x multiplexing Four LCD memory banks for screen scrolling LCD voltages generated internally or with external resistors Internal adjustable drive voltages up to 5 V independent of power supply level On-chip peripherals Two independent UART interfaces SPI or I2C Watchdog timer Power supply management with user-selectable levels Memory: 62 kB flash memory, 2.256 kB RAM Development tools Single-pin emulation IDE-based assembly and C-source debugging
Wide supply voltage operation: 2.4 V to 3.7 V Internal bipolar switch between regulated and battery inputs Ultralow power operation with power saving modes (PSM) Full operation: 4 mA to 1.6 mA (PLL clock dependent) Battery mode: 3.2 mA to 400 A (PLL clock dependent) Sleep mode Real-time clock (RTC) mode: 1.5 A RTC and LCD mode: 27 A (LCD charge pump enabled) Reference: 1.2 V 0.1% (10 ppm/C drift) 64-lead RoHS package options Low profile quad flat package (LQFP) Operating temperature range: -40C to +85C
ENERGY MEASUREMENT FEATURES
Proprietary analog-to-digital converters (ADCs) and digital signal processing (DSP) provide high accuracy active (WATT), reactive (VAR), and apparent energy (VA) measurement Less than 0.1% error on active energy over a dynamic range of 1000 to 1 @ 25C Less than 0.5% error on reactive energy over a dynamic range of 1000 to 1 @ 25C (ADE5569 and ADE5169 only) Less than 0.5% error on root mean square (rms) measurements over a dynamic range of 500 to 1 for current (Irms) and 100 to 1 for voltage (Vrms) @ 25C Supports IEC 62053-21, IEC 62053-22, IEC 62053-23, EN 50470-3 Class A, Class B, and Class C, and ANSI C12-16 Differential input with programmable gain amplifiers (PGAs) supports shunts, current transformers, and di/dt current sensors (ADE5569 and ADE5169 only) Two current inputs for antitamper detection in the ADE5166/ADE5169 High frequency outputs proportional to Irms, active, reactive, or apparent power (AP)
Table 1. Features Available on Each Part
Feature Antitamper WATT, VA, Irms, Vrms VAR di/dt Sensor Part No. ADE5166, ADE5169 ADE5166, ADE5169, ADE5566, ADE5569 ADE5169, ADE5569 ADE5169, ADE5569
Rev. PrB
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ADE5166/ADE5169/ADE5566/ADE5569 TABLE OF CONTENTS
General Features ............................................................................... 1 Energy Measurement Features........................................................ 1 Microprocessor Features.................................................................. 1 General Description ......................................................................... 4 Functional Block Diagrams ............................................................. 4 Specifications..................................................................................... 6 Energy Metering ........................................................................... 6 Analog Peripherals ....................................................................... 7 Digital Interface ............................................................................ 8 Timing Specifications ................................................................ 10 Absolute Maximum Ratings.......................................................... 15 Thermal Resistance .................................................................... 15 ESD Caution ................................................................................ 15 Pin Configuration and Function Descriptions ........................... 16 Terminology .................................................................................... 18 SFR Mapping ................................................................................... 19 Power Management ........................................................................ 21 Power Management Register Details ....................................... 21 Power Supply Architecture ........................................................ 24 Battery Switchover...................................................................... 24 Power Supply Management Interrupt (PSM) ......................... 25 Using the Power Supply Features ............................................. 27 Operating Modes ............................................................................ 29 PSM0 (Normal Mode) ............................................................... 29 PSM1 (Battery Mode) ................................................................ 29 PSM2 (Sleep Mode).................................................................... 29 3.3 V Peripherals and Wake-Up Events ................................... 30 Transitioning Between Operating Modes ............................... 31 Using the Power Management Features .................................. 31 Energy Measurement ..................................................................... 33 Access to Energy Measurement SFRs ...................................... 33 Access to Internal Energy Measurement Registers ................ 33 Energy Measurement Registers ................................................ 36 Energy Measurement Internal Registers Details .................... 37 Interrupt Status/Enable SFRs .................................................... 40 Analog Inputs .............................................................................. 42 Analog-to-Digital Conversion .................................................. 43 Fault Detection .......................................................................... 46 di/dt Current Sensor and Digital Integrator for the ADE5569/ADE5169 ................................................................... 47
1
Preliminary Technical Data
Power Quality Measurements................................................... 49 Phase Compensation ................................................................. 51 RMS Calculation ........................................................................ 51 Active Power Calculation .......................................................... 54 Active Energy Calculation ........................................................ 56 Reactive Power Calculation for the ADE5569/ADE5169 ..... 59 Reactive Energy Calculation for the ADE5569/ADE5169 ... 60 Apparent Power Calculation ..................................................... 64 Apparent Energy Calculation ................................................... 64 Ampere-Hour Accumulation ................................................... 66 Energy-to-Frequency Conversion............................................ 66 Energy Register Scaling ............................................................. 67 Energy Measurement Interrupts .............................................. 67 Temperature, Battery, and Supply Voltage Measurements........ 68 Temperature Measurement ....................................................... 70 Battery Measurement ................................................................. 70 External Voltage Measurement ................................................ 71 8052 MCU Core Architecture....................................................... 73 MCU registers ............................................................................. 73 Basic 8052 Registers ................................................................... 75 Standard 8052 SFRs.................................................................... 77 Memory Overview ..................................................................... 77 Addressing Modes ...................................................................... 78 Instruction Set ............................................................................ 80 Read-Modify-Write Instructions ............................................. 82 Instructions That Affect Flags .................................................. 82 Dual Data Pointers ......................................................................... 84 Interrupt System ............................................................................. 85 Standard 8052 Interrupt Architecture ..................................... 85 Interrupt Architecture ............................................................... 85 Interrupt Registers...................................................................... 85 Interrupt Priority ........................................................................ 86 Interrupt Flags ............................................................................ 87 Interrupt Vectors ........................................................................ 89 Interrupt Latency........................................................................ 89 Context Saving ............................................................................ 89 Watchdog Timer ............................................................................. 90 LCD Driver ...................................................................................... 92 LCD Registers ............................................................................. 92 LCD Setup ................................................................................... 95
Rev. PrB | Page 2 of 148
Preliminary Technical Data
LCD Timing and Waveforms ....................................................95 Blink Mode ...................................................................................96 Scrolling Mode ............................................................................96 Display Element Control ............................................................96 Voltage Generation .....................................................................97 LCD External Circuitry ..............................................................97 LCD Function in PSM2 ..............................................................98 Flash Memory ..................................................................................99 Flash Memory Overview ............................................................99 Flash Memory Organization......................................................99 Using the Flash Memory ......................................................... 100 Protecting the Flash Memory ................................................. 103 In Circuit Programming ......................................................... 105 Timers ............................................................................................ 106 Timer Registers......................................................................... 106 Timer 0 and Timer 1 ................................................................ 108 Timer 2 ...................................................................................... 109 PLL ................................................................................................. 111 PLL Registers ............................................................................ 111 RTC--Real-Time Clock .............................................................. 112 Access to RTC SFR ................................................................... 112 Access to Internal RTC Registers ........................................... 112 RTC SFR Register List ............................................................. 113 RTC Registers ........................................................................... 116 RTC Calendar ........................................................................... 117 RTC Interrupts ......................................................................... 118 RTC Crystal Compensation.................................................... 119 RTC Temperature Compensation .......................................... 119 UART Serial Interface .................................................................. 121 UART Registers ........................................................................ 121
2
ADE5166/ADE5169/ADE5566/ADE5569
UART Operation Modes ..........................................................124 UART Baud Rate Generation ..................................................125 UART Additional Features ......................................................127 UART2 Serial Interface.................................................................128 UART SFR Register List ...........................................................128 UART2 Operation Mode .........................................................130 UART Baud Rate Generation ..................................................130 UART Additional Features ......................................................131 Serial Peripheral Interface (SPI) ..................................................132 SPI Registers ..............................................................................132 SPI Pins.......................................................................................135 SPI Master Operating Modes ..................................................136 SPI Interrupt and Status Flags .................................................137 I C-Compatible Interface .............................................................138 Serial Clock Generation ...........................................................138 Slave Addresses..........................................................................138 I2C Registers ...............................................................................138 Read and Write Operations .....................................................139 I2C Receive and Transmit FIFOs.............................................140 I/O Ports .........................................................................................141 Parallel I/O .................................................................................141 I/O Registers ..............................................................................142 Port 0...........................................................................................145 Port 1...........................................................................................145 Port 2...........................................................................................145 Determining the Version of the ADE5166/ADE5169/ADE5566/ADE5569 ................................146 Outline Dimensions ......................................................................147 Ordering Guide .........................................................................147
Rev. PrB | Page 3 of 148
ADE5166/ADE5169/ADE5566/ADE5569
GENERAL DESCRIPTION
The ADE5166/ADE5169/ADE5566/ADE55691 integrate Analog Devices, Inc., energy (ADE) metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, a full RTC, an LCD driver, and all the peripherals to make an electronic energy meter with an LCD display in a single part. The ADE measurement core includes active, reactive, and apparent energy calculations, as well as voltage and current rms measurements. This information is ready to use for energy billing by using built-in energy scalars. Many power line supervisory features such as SAG, peak, and zero crossing are included in the energy measurement DSP to simplify energy meter design.
Preliminary Technical Data
The microprocessor functionality includes a single-cycle 8052 core, a full real-time clock with a power supply backup pin, two independent UART interfaces, and an SPI or I2C(R) interface. The ready-to-use information from the ADE core reduces the program memory size requirement, making it easy to integrate complicated design into 62 kB of flash memory. The ADE5166/ADE5169/ADE5566/ADE5569 also include a 108-/104-segment LCD driver with the capability to store up to 4 LCD screens in memory. This driver generates voltages capable of driving LCDs up to 5 V.
FUNCTIONAL BLOCK DIAGRAMS
P0.3 (CF2) P0.4 (MOSI/SDATA) P0.5 (MISO/ZX) P0.6 (SCLK/T0) P0.7 (SS/T1) P0.2/(CF1/RTCCAL) P0.0 (BCTRL/INT1) P1.2/ZX (FP25/ZX) P1.3 (T2EX/FP24) P1.4 (T2/FP23)
6 7
MOSI/SDATA
P0.1 (FP19)
57
43 42
38 39 40 41
39 38 7
6
45 11 43 42 41 40 39 38
37 36 5
P1.5 (FP22)
8
P1.6 (FP21) P1.7 (FP20)
9 10 12 P2.0 (FP18) 13 P2.1 (FP17)
1.20V REF IP 52 IN 53 + PGA1 - ADC
SPI/I2C SERIAL INTERFACE
3 x 16-BIT COUNTER TIMERS
ADE5566/ADE5569
P1.0 (RxD) P1.1 (TxD)
REFIN/OUT
SCLK
MISO
T2EX
CF1
CF2
SS
T0
T1
T2
14 P2.2 (FP16) 44 P2.3 (SDEN) 19 16
LCDVP1 LCDVP2 LCDVA LCDVB LCDVC COM0
3V/5V LCD CHARGE PUMP ENERGY MEASUREMENT DSP
18 17 15 4
...
COM3
VP 49 VN 50 DGND 63 AGND 54
+ PGA2 -
ADC PROGRAM MEMORY 62kB FLASH USER RAM 256 BYTES TEMP ADC USER XRAM 2kB SINGLE CYCLE 8052 MCU WATCHDOG TIMER
104 SEGMENTS LCD DRIVER
...
1
35 FP0
...
FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25 FP26
07411-001
TEMP SENSOR BATTERY ADC
VBAT 58
UART2 TIMER DOWNLOADER DEBUGGER UART TIMER UART SERIAL PORT
36 37
POWER SUPPLY CONTROL AND MONITORING
1-PIN EMULATOR
VSW ADC POR LDO LDO
PLL UART2 SERIAL PORT
RTC
OSC
64
60
61
62
59
56
51
44
38
47
46
48
45
VSWOUT
RESET
XTAL1
XTAL2
EA
VINTD
VINTA
TxD
VDCIN
SDEN/TxD2
Figure 1. ADE5566/ADE5569 Functional Block Diagram
1
Patents pending.
Rev. PrB | Page 4 of 148
RxD2
INT0
INT1
VDD
RxD
.. .
14 13 12 11 10 9 8 7 6 5 55
20 FP15
Preliminary Technical Data
P0.2 (CF1/RTCCAL) P0.0 (BCTRL/INT1) MOSI/SDATA P0.1 (FP19)
ADE5166/ADE5169/ADE5566/ADE5569
P0.3 (CF2) P0.4 (MOSI/SDATA) P0.5 (MISO/ZX) P0.6 (SCLK/T0) P0.7 (SS/T1) P1.0 (RxD) P1.1 (TxD) P1.2 (FP25/ZX) P1.3 (T2EX/FP24) P1.4 (T2/FP23)
37 36 5 6 7
P1.5 (FP22)
8
57
43 42
38 39 40 41
39 38 7
6
45 11 43 42 41 40 39 38
P1.6 (FP21) P1.7 (FP20)
9 10 12 13
REFIN/OUT
SCLK
MISO
T2EX
CF1
CF2
SS
T0
T1
T2
P2.0 (FP18) P2.1 (FP17) P2.2 (FP16) P2.3 (SDEN) LCDVP1 LCDVP2 LCDVA LCDVB LCDVC COM0
1.20V REF IPA 52 IN 53 IPB 55 VP 49 VN 50 DGND 63 AGND 54 + PGA1 - + PGA1 - + PGA2 - ADC
SPI/I2C SERIAL INTERFACE
3 x 16-BIT COUNTER TIMERS
ADE5166/ADE5169
14 44 19 16
3V/5V LCD CHARGE PUMP ENERGY MEASUREMENT DSP 104-SEGMENT LCD DRIVER PROGRAM MEMORY 62kB FLASH USER RAM 256 BYTES SINGLE CYCLE 8052 MCU WATCHDOG TIMER
18 17 15 4
ADC
...
COM3 FP0
ADC
...
1 35
...
FP15 FP16 FP17 FP18 FP19 FP20 FP21 FP22 FP23 FP24 FP25
TEMP SENSOR BATTERY ADC
TEMP ADC
USER XRAM 2kB
VBAT 58
UART2 TIMER DOWNLOADER DEBUGGER UART TIMER UART SERIAL PORT
36 37
POWER SUPPLY CONTROL AND MONITORING
1-PIN EMULATOR
VSW ADC POR LDO LDO
PLL UART2 SERIAL PORT
RTC
OSC
64
60
61
62
59
56
51
44
38
47
46
48
45
VSWOUT
RESET
XTAL1
XTAL2
EA
VINTD
VINTA
TxD
VDCIN
SDEN/TxD2
RxD2
INT0
INT1
VDD
RxD
.. .
20 14 13 12 11 10 9 8 7
6
5
Figure 2. ADE5166/ADE5169 Functional Block Diagram
Rev. PrB | Page 5 of 148
07411-201
ADE5166/ADE5169/ADE5566/ADE5569 SPECIFICATIONS
Preliminary Technical Data
VDD = 3.3 V 5%, AGND = DGND = 0 V, on-chip reference XTAL = 32.768 kHz, TMIN to TMAX = -40C to +85C, unless otherwise noted.
ENERGY METERING
Table 2.
Parameter MEASUREMENT ACCURACY1 Phase Error Between Channels PF = 0.8 Capacitive PF = 0.5 Inductive Active Energy Measurement Error2 AC Power Supply Rejection2 Output Frequency Variation DC Power Supply Rejection2 Output Frequency Variation Active Energy Measurement Bandwidth1 Reactive Energy Measurement Error2, 3 Vrms Measurement Error2 Vrms Measurement Bandwidth1 Irms Measurement Error2 Irms Measurement Bandwidth1 ANALOG INPUTS Maximum Signal Levels ADE5566/ADE5569 ADE5166/ADE5169 Input Impedance (DC) ADC Offset Error2 Gain Error2 Current Channel Voltage Channel Gain Error Match CF1 AND CF2 PULSE OUTPUT Maximum Output Frequency Duty Cycle Active High Pulse Width FAULT DETECTION4 Fault Detection Threshold Inactive Input Active Input Input Swap Threshold Inactive Input > Active Input Accuracy Fault Mode Operation IPA Active, IPB = AGND IPB Active, IPA = AGND Fault Detection Delay Swap Delay
1 2
Min
Typ
Max
Unit
Test Conditions/Comments
0.05 0.05 0.1 0.01 0.01 8 0.5 0.5 3.9 0.5 3.9
Degrees Degrees % of reading % % kHz % of reading % of reading kHz % of reading kHz
Phase lead: 37 Phase lag: 60 Over a dynamic range of 1000 to 1 @ 25C VDD = 3.3 V + 100 mV rms/120 Hz IPx = VP = 100 mV rms VDD = 3.3 V 117 mV dc
Over a dynamic range of 1000 to 1 @ 25C Over a dynamic range of 100 to 1 @ 25C Over a dynamic range of 500 to 1 @ 25C
400 400 250 770 10 1 3 3 0.2 21.1 50 90
mV peak mV peak mV peak k mV mV % % % kHz % ms
VP - VN differential input IP - IN differential input IPA - IN and IPB - IN differential inputs PGA1 = PGA2 = 1 PGA1 = 16 IPA = IPB = 0.4 V dc or IP = 0.4 dc Voltage channel = 0.4 V dc
VP - VN = 400 mV peak, IPA - IN = 250 mV, PGA1 = 2 sine wave If CF1 or CF2 frequency, >5.55 Hz If CF1 or CF2 frequency, <5.55 Hz
6.25 6.25 0.1 0.1 3 3
%, of active % of active % of reading % of reading Seconds Seconds
IPA or IPB active IPA or IPB active Over a dynamic range of 500 to 1 Over a dynamic range of 500 to 1
These specifications are not production tested but are guaranteed by design and/or characterization data on production release. See the Terminology section for definition. 3 This function is not available in the ADE5566 and the ADE5166. 4 This function is not available in the ADE5566 and the ADE5569.
Rev. PrB | Page 6 of 148
Preliminary Technical Data
ANALOG PERIPHERALS
Table 3.
Parameter INTERNAL ADCs (BATTERY, TEMPERATURE, VDCIN) Power Supply Operating Range No Missing Codes1 Conversion Delay2 ADC Gain VDCIN Measurement VBAT Measurement Temperature Measurement ADC Offset VDCIN Measurement at 3 V VBAT Measurement at 3.7 V Temperature Measurement at 25C VDCIN Analog Input Maximum Signal Levels Input Impedance (DC) Low VDCIN Detection Threshold POWER-ON RESET (POR) VDD POR Detection Threshold POR Active Timeout Period VSWOUT POR Detection Threshold POR Active Timeout Period VINTD POR Detection Threshold POR Active Timeout Period VINTA POR Detection Threshold POR Active Timeout Period BATTERY SWITCH OVER Voltage Operating Range (VSWOUT) VDD to VBAT Switching Switching Threshold (VDD) Switching Delay VBAT to VDD Switching Switching Threshold (VDD) Switching Delay VSWOUT To VBAT Leakage Current LCD, CHARGE PUMP ACTIVE Charge Pump Capacitance Between LCDVP1 and LCDVP2 LCDVA, LCDVB, LCDVC Decoupling Capacitance LCDVA LCDVB LCDVC V1 Segment Line Voltage V2 Segment Line Voltage V3 Segment Line Voltage DC Voltage Across Segment and COMx Pin Min 2.4 8 38 15.3 14.6 0.78 206 205 129 3.3 1 1.2 Typ
ADE5166/ADE5169/ADE5566/ADE5569
Max 3.7
Unit V Bits s mV/LSB mV/LSB C/LSB LSB LSB LSB V M V
Test Conditions/Comments Measured on VSWOUT
2.7 33 2 20 2.1 16 2.05 120 3.3 2.7 10 30 2.7 30 10 100 470 1.75 3.5 5.3 LCDVA - 0.1 LCDVB - 0.1 LCDVC - 0.1 50
Rev. PrB | Page 7 of 148
V ms V ms V ms V ms V V ns ms V ms nA nF nF V V V V V V mV
When VDD to VBAT switch activated by VDD When VDD to VBAT switch activated by VDCIN
Based on VDD > 2.75 V VBAT = 0 V, VSWOUT = 3.43 V, TA = 25C
LCDVA LCDVB LCDVC
1/3 bias mode 1/3 bias mode Current on segment line = -2 A Current on segment line = -2 A Current on segment line = -2 A LCDVC - LCDVB, LCDVC - LCDVA, or LCDVB - LCDVA
ADE5166/ADE5169/ADE5566/ADE5569
Parameter LCD, RESISTOR LADDER ACTIVE Leakage Current V1 Segment Line Voltage V2 Segment Line Voltage V3 Segment Line Voltage ON-CHIP REFERENCE Reference Error Power Supply Rejection Temperature Coefficient1
1 2
Preliminary Technical Data
Typ 20 Max Unit nA V V V mV dB ppm/C Test Conditions/Comments 1/2 and 1/3 bias modes, no load Current on segment line = -2 A Current on segment line = -2 A Current on segment line = -2 A TA = 25C
Min
LCDVA - 0.1 LCDVB - 0.1 LCDVC - 0.1 0.9 80 10
LCDVA LCDVB LCDVC
These specifications are not production tested but are guaranteed by design and/or characterization data on production release. Delay between ADC conversion request and interrupt set.
DIGITAL INTERFACE
Table 4.
Parameter LOGIC INPUTS All Inputs Except XTAL1, XTAL2, BCTRL, INT0, INT1, RESET Input High Voltage, VINH Input Low Voltage, VINL BCTRL, INT0, INT1, RESET Input High Voltage, VINH Input Low Voltage, VINL Input Currents RESET Port 0, Port 1, Port 2 Input Capacitance FLASH MEMORY Endurance1 Data Retention2 CRYSTAL OSCILLATOR Crystal Equivalent Series Resistance Crystal Frequency XTAL1 Input Capacitance XTAL2 Output Capacitance MCU CLOCK RATE (fCORE) LOGIC OUTPUTS Output High Voltage, VOH ISOURCE Output Low Voltage, VOL3 ISINK START-UP TIME4 PSM0 Power-On Time From Power Saving Mode 1 (PSM1) PSM1 PSM0 From Power Saving Mode 2 (PSM2) PSM2 PSM1 PSM2 PSM0 Min Typ Max Unit Test Conditions/Comments
2.0 0.4 1.3 0.4 100 100 -3.75 10 10,000 20 40 32.768 12 12 4.096 32 2.4 80 0.4 2 448 130 48 186
V V V V nA nA A pF Cycles Years k kHz pF pF MHz kHz V A V mA ms ms ms ms RESET = VSWOUT = 3.3 V Internal pull-up disabled, input = 0 V or VSWOUT Internal pull-up enabled, input = 0 V, VSWOUT = 3.3 V All digital inputs
TJ = 85C
Crystal = 32.768 kHz and CD[2:0] = 0 Crystal = 32.768 kHz and CD[2:0] = 0b111 VDD = 3.3 V 5% VDD = 3.3 V 5%
VDD at 2.75 V to PSM0 code execution VDD at 2.75 V to PSM0 code execution Wake-up event to PSM1 code execution VDD at 2.75 V to PSM0 code execution
Rev. PrB | Page 8 of 148
Preliminary Technical Data
Parameter POWER SUPPLY INPUTS VDD VBAT INTERNAL POWER SUPPLY SWITCH (VSWOUT) VBAT to VSWOUT On Resistance VDD to VSWOUT On Resistance VBAT VDD Switching Open Time BCTRL State Change and Switch Delay VSWOUT Output Current Drive POWER SUPPLY OUTPUTS VINTA VINTD VINTA Power Supply Rejection VINTD Power Supply Rejection POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) Min Typ 3.3 3.3 22 10.2 40 18 1 2.5 2.5 60 50 4 2.1 1.6 3.2 3 Current in PSM1 Current in PSM2 POWER SUPPLY CURRENTS Current in Normal Mode (PSM0)
1 2 3
ADE5166/ADE5169/ADE5566/ADE5569
Max Unit V V ns s mA V V dB dB mA mA mA mA mA mA A A A mA fCORE = 4.096 MHz, LCD and meter active fCORE = 1.024 MHz, LCD and meter active fCORE = 32.768 kHz, LCD and meter active fCORE = 4.096 MHz, meter DSP active, metering ADC powered down fCORE = 4.096 MHz, metering ADC and DSP powered down fCORE = 4.096 MHz, LCD active, VBAT = 3.7 V fCORE = 1.024 MHz, LCD active LCD active with charge pump at 3.3 V + RTC RTC only, TA = 25C, VBAT = 3.3 V fCORE = 4.096 MHz, LCD and meter active VBAT = 2.4 V VDD = 3.13 V Test Conditions/Comments
3.2 880 38 1.5 4
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at -40C, +25C, +85C, and +125C. Retention lifetime equivalent at junction temperature (TJ) = 85C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature. Test carried out with all the I/Os set to a low output level. 4 Delay between power supply valid and execution of first instruction by 8052 core.
Rev. PrB | Page 9 of 148
ADE5166/ADE5169/ADE5566/ADE5569
TIMING SPECIFICATIONS
AC inputs during testing were driven at VSWOUT - 0.5 V for Logic 1 and 0.45 V for Logic 0. Timing measurements were made at VIH minimum for Logic 1 and VIL maximum for Logic 0, as shown in Figure 3.
Preliminary Technical Data
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs as shown in Figure 3. CLOAD for all outputs = 80 pF, unless otherwise noted. VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
VLOAD - 0.1V VLOAD VLOAD + 0.1V TIMING REFERENCE POINTS VLOAD - 0.1V VLOAD - 0.1V
07411-002
VSWOUT - 0.5V
0.45V
0.2VSWOUT + 0.9V TEST POINTS 0.2VSWOUT - 0.1V
VLOAD
Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameter
Parameter tCK tCKL tCKH tCKR tCKF 1/tCORE
1
Description XTAL1 period XTAL1 width low XTAL1 width high XTAL1 rise time XTAL1 fall time Core clock frequency1
Min
32.768 kHz External Crystal Typ Max 30.52 6.26 6.26 9 9 1.024
Unit s s s ns ns MHz
The ADE5166/ADE5169/ADE5566/ADE5569 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR (see Table 25).
Table 6. I2C-Compatible Interface Timing Parameters (400 kHz)
Parameter tBUF tL tH tSHD tDSU tDHD tRSU tPSU tR tF tSUP1
1
Description Bus-free time between stop condition and start condition SCLK low pulse width SCLK high pulse width Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Rise time of both SCLK and SDATA Fall time of both SCLK and SDATA Pulse width of spike suppressed
Typ 1.3 1.36 1.14 251.35 740 400 12.5 400 200 300 50
Unit s s s s ns ns ns ns ns ns ns
Input filtering on both the SCLK and SDATA inputs suppresses noise spikes less than 50 ns.
tBUF
SDATA (I/O) MSB
tSUP
LSB ACK
tR
MSB
tDSU tPSU
SCLK (I)
PS STOP START CONDITION CONDITION
tDHD tSHD
1 2 TO 7 8
tDSU tH
9
tDHD tRSU
tF tR
1
S(R)
tL
tSUP
REPEATED START
Figure 4. I2C-Compatible Interface Timing
Rev. PrB | Page 10 of 148
07411-003
tF
Preliminary Technical Data
Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters
Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF
1
ADE5166/ADE5169/ADE5566/ADE5569
Min 2SPIR x tCORE1 2SPIR x tCORE1 0 tCORE1 19 19 19 19 Typ Max Unit ns ns ns ns ns ns ns ns ns
Description SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time
3 x tCORE1
tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz.
SCLK (SPICPOL = 0) SCLK (SPICPOL = 1)
tSH
tSL tSR tSF
tDAV
MOSI MSB
tDF
tDR
BITS [6:1] LSB
MISO
MSB IN
BITS [6:1]
LSB IN
07411-004
tDSU
tDHD
Figure 5. SPI Master Mode Timing (SPICPHA = 1)
Rev. PrB | Page 11 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters
Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF
1
Preliminary Technical Data
Min 2SPIR x tCORE1 2SPIR x tCORE1 Typ (SPIR + 1) x tCORE1 (SPIR + 1) x tCORE1 Max Unit ns ns ns ns ns ns ns ns ns ns
Description SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data output setup before SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time
3 x tCORE1 75 0 tCORE1 19 19 19 19
tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz.
SCLK (SPICPOL = 0) SCLK (SPICPOL = 1)
tSH
tSL tSR tSF
tDAV tDOSU
MOSI MSB BITS [6:1] LSB
tDF
tDR
MISO
MSB IN
BITS [6:1]
LSB IN
07411-005
tDSU
tDHD
Figure 6. SPI Master Mode Timing (SPICPHA = 0)
Rev. PrB | Page 12 of 148
Preliminary Technical Data
Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters
Parameter tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS
1
ADE5166/ADE5169/ADE5566/ADE5569
Min 145 6 x tCORE1 6 x tCORE1 0 2 x tCORE1 + 0.5 s 19 19 19 19 0 Typ Max Unit ns ns ns ns ns s ns ns ns ns ns
Description SS to SCLK edge SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time SS high after SCLK edge
25
tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz.
SS
tSS
tSFS
SCLK (SPICPOL = 0)
tSH
tSL tSR tSF
SCLK (SPICPOL = 1)
tDAV
MISO MSB
tDF
tDR
BITS [6:1] LSB
MOSI
MSB IN
BITS [6:1]
LSB IN
07411-006
tDSU
tDHD
Figure 7. SPI Slave Mode Timing (SPICPHA = 1)
Rev. PrB | Page 13 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters
Parameter tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOSS tSFS
1
Preliminary Technical Data
Min 145 6 x tCORE1 6 x tCORE1 0 2 x tCORE1+ 0.5 s 19 19 19 19 0 0 Typ Max Unit ns ns ns ns ns s ns ns ns ns ns ns
Description SS to SCLK edge SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time Data output valid after SS edge SS high after SCLK edge
25
tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz.
SS
tSS
tSFS
SCLK (SPICPOL = 0)
tSH
SCLK (SPICPOL = 1)
tSL tSR tSF
tDAV tDOSS
MISO MSB
tDF
tDR
BITS [6:1] LSB
MOSI
MSB IN
BITS [6:1]
LSB IN
07411-007
tDSU
tDHD
Figure 8. SPI Slave Mode Timing (SPICPHA = 0)
Rev. PrB | Page 14 of 148
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 11.
Parameter VDD to DGND VBAT to DGND VDCIN to DGND Input LCD Voltage to AGND, LCDVA, LCDVB, LCDVC1 Analog Input Voltage to AGND, VP, VN, IPA, and IN Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range (Industrial) Storage Temperature Range 64-Lead LQFP, Power Dissipation Lead Temperature Soldering Time
1
ADE5166/ADE5169/ADE5566/ADE5569
Rating -0.3 V to +3.7 V -0.3 V to +3.7 V -0.3 V to VSWOUT + 0.3 V -0.3 V to VSWOUT + 0.3 V -2 V to +2 V -0.3 V to VSWOUT + 0.3 V -0.3 V to VSWOUT + 0.3 V -40C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 12. Thermal Resistance
Package Type 64-Lead LQFP JA 60 JC 20.5 Unit C/W
ESD CAUTION
300C 30 sec
When used with external resistor divider.
Rev. PrB | Page 15 of 148
ADE5166/ADE5169/ADE5566/ADE5569 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFIN/OUT RESET FP26/IPB VSWOUT DGND AGND VDCIN VINTD VINTA IP/IPA VBAT VDD EA VN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Preliminary Technical Data
COM3/FP27 COM2/FP28 COM1 COM0 P1.2/FP25/ZX P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21
VP
IN
1 2 3 4 5 6 7 8 9 PIN 1
48 47 46 45 44 43 42
INT0 XTAL1 XTAL2 BCTRL/INT1/P0.0 SDEN/P2.3/TxD2 P0.2/CF1/RTCCAL P0.3/CF2 P0.4/MOSI/SDATA P0.5/MISO/ZX P0.6/SCLK/T0 P0.7/SS/T1/RxD2 P1.0/RxD P1.1/TxD FP0 FP1 FP2
ADE5166/ADE5169/ADE5566/ADE5569
TOP VIEW (Not to Scale)
41 40 39 38 37 36 35 34 33
P1.7/FP20 10 P0.1/FP19 11 P2.0/FP18 12 P2.1/FP17 13 P2.2/FP16 14 LCDVC 15 LCDVP2 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LCDVA
FP9
FP8
FP7
FP6
FP5
FP4
FP15
FP14
FP13
FP12
FP11
LCDVP1
LCDVB
FP10
FP3
Figure 9. Pin Configuration
Table 13. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17, 18 19 35 to 20 36 37 38 39 40 Mnemonic COM3/FP27 COM2/FP28 COM1 COM0 P1.2/FP25/ZX P1.3/T2EX/FP24 P1.4/T2/FP23 P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16 LCDVC LCDVP2 LCDVB, LCDVA LCDVP1 FP0 to F15 P1.1/TxD P1.0/RxD P0.7/SS/T1/RxD2 P0.6/SCLK/T0 P0.5/MISO/ZX Description Common Output 3 or LCD Segment Output 27. COM3 is used for LCD backplane. Common Output 2 or LCD Segment Output 28. COM2 is used for LCD backplane. Common Output 1. COM1 is used for LCD backplane. Common Output 0. COM0 is used for LCD backplane. General-Purpose Digital I/O Port 1.2 or LCD Segment Output 25/ZX Output General-Purpose Digital I/O Port 1.3, Timer 2 Control Input, or LCD Segment Output 24. General-Purpose Digital I/O Port 1.4, Timer 2 Input, or LCD Segment Output 23. General-Purpose Digital I/O Port 1.5 or LCD Segment Output 22. General-Purpose Digital I/O Port 1.6 or LCD Segment Output 21. General-Purpose Digital I/O Port 1.7 or LCD Segment Output 20. General-Purpose Digital I/O Port 0.1 or LCD Segment Output 19. General-Purpose Digital I/O Port 2.0 or LCD Segment Output 18. General-Purpose Digital I/O Port 2.1 or LCD Segment Output 17. General-Purpose Digital I/O Port 2.2 or LCD Segment Output 16. Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor. Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD charge pump device. Output Port for LCD Levels. These pins should be decoupled with a 470 nF capacitor. Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD charge pump device. LCD Segment Output 0 to LCD Segment Output 15. General-Purpose Digital I/O Port 1.1 or Transmitter Data Output (Asynchronous). General-Purpose Digital I/O Port 1.0 or Receiver Data Input (Asynchronous). General-Purpose Digital I/O Port 0.7, Slave Select when SPI is in Slave Mode, or Timer 1 Input/Receive Data Input 2 (Asynchronous) General-Purpose Digital I/O Port 0.6, Clock Output for I2C or SPI Port, or Timer 0 Input. General-Purpose Digital I/O Port 0.5 or Data Input for SPI Port/ZX Output
Rev. PrB | Page 16 of 148
07411-010
Preliminary Technical Data
Pin No. 41 42 43 Mnemonic P0.4/MOSI/SDATA P0.3/CF2 P0.2/CF1/RTCCAL
ADE5166/ADE5169/ADE5566/ADE5569
44
SDEN/P2.3/TxD2
45
BCTRL/INT1/P0.0
46
XTAL2
47
XTAL1
48 49, 50 51
INT0 VP, VN EA
52, 53 54 55
IP/IPA, IN AGND FP26 or IPB
56 57
RESET REFIN/OUT
58 59 60
VBAT VINTA VDD
61
VSWOUT
62 63 64
VINTD DGND VDCIN
Description General-Purpose Digital I/O Port 0.4, Data Output for SPI Port, or I2C-Compatible Data Line. General-Purpose Digital I/O Port 0.3 or Calibration Frequency Logic Output 2. The CF2 logic output gives instantaneous active, reactive, Irms, or apparent power information. General-Purpose Digital I/O Port 0.2, Calibration Frequency Logic Output 1, or RTC Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, Irms, or apparent power information. The RTCCAL logic output gives access to the calibrated RTC output. Serial Download Mode Enable or Digital Output Pin P2.3. This pin is used to enable serial download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3)/ Transmitter Data Output 2 (asynchronous). Digital Input for Battery Control, External Interrupt Input 1, or General-Purpose Digital I/O Port 0.0. This logic input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left open, the connection between VDD or VBAT and VSWOUT is selected internally. A crystal can be connected across this pin and XTAL1 (see XTAL1 pin description) to provide a clock source for the ADE5166/ADE5169/ADE5566/ADE5569. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin. An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE5166/ADE5169/ADE5566/ADE5569. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin. External Interrupt Input 0. Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum differential level of 400 mV for specified operation. This channel also has an internal PGA. This pin is used as an input for emulation. When held high, this input enables the device to fetch code from internal program memory locations. The ADE5166/ADE5169/ADE5566/ADE5569 do not support external code memory. This pin should not be left floating. Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of 400 mV for specified operation. This channel also has an internal PGA. This pin provides the ground reference for the analog circuitry. LCD Segment Output 26 (FP26) for ADE5566 and ADE5569 or Analog Input for Second Current Channel (IPB) for ADE5166 and ADE5169. This input is fully differential with a maximum differential level of 400 mV referred to IN for specified operation. This channel also has an internal PGA. Reset Input, Active Low. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 1.2 V 0.1% and a typical temperature coefficient of 50 ppm/C maximum. This pin should be decoupled with a 1 F capacitor in parallel with a ceramic 100 nF capacitor. Power Supply Input from the Battery with a 2.4 V to 2.7 V Range. This pin is connected internally to VDD when the battery is selected as the power supply for the ADE5166/ADE5169/ADE5566/ADE5569. This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VDD when the regulator is selected as the power supply for the ADE5166/ADE5169/ADE5566/ADE5569. This pin should be decoupled with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the ADE5166/ADE5169/ADE5566/ADE5569. This pin should be decoupled with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. This pin provides the ground reference for the digital circuitry. Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to AGND. This pin is used to monitor the preregulated dc voltage.
Rev. PrB | Page 17 of 148
ADE5166/ADE5169/ADE5566/ADE5569 TERMINOLOGY
Measurement Error The error associated with the energy measurement made by the ADE5166/ADE5169/ADE5566/ADE5569 is defined by the following formula: Percentage Errror =
Preliminary Technical Data
For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied 5%. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error ADC offset error is the dc offset associated with the analog inputs to the ADCs. It means that, with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection. However, when HPF1 is switched on, the offset is removed from the current channel, and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration (see the Analog Inputs section). Gain Error Gain error is the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and the Voltage Channel ADC section). It is measured for each of the gain settings on the current channel (1, 2, 4, 8, and 16). The difference is expressed as a percentage of the ideal code.
Energy Register - True Energy x 100% True Energy
Phase Error Between Channels The digital integrator and the high-pass filter (HPF) in the current channel have a nonideal phase response. To offset this phase response and equalize the phase response between channels, two phase correction networks are placed in the current channel: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between current channel and voltage channel to within 0.1 over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within 0.4 over a range of 45 Hz to 65 Hz. Power Supply Rejection (PSR) PSR quantifies the ADE5166/ADE5169/ADE5566/ADE5569 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac (100 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading (see the Measurement Error definition).
Rev. PrB | Page 18 of 148
Preliminary Technical Data SFR MAPPING
Table 14. SFR Mapping
Mnemonic INTPR SCRATCH4 SCRATCH3 SCRATCH2 SCRATCH1 BATVTH STRBPER IPSMF TEMPCAL RTCCOMP BATPR PERIPH DIFFPROG B VDCINADC SBAUD2 LCDSEGE2 IPSME SBUF2 SPISTAT SPI2CSTAT SPIMOD2 I2CADR SPIMOD1 I2CMOD WAV2H WAV2M WAV2L WAV1H WAV1M WAV1L SCON2 ACC BATADC MIRQSTH MIRQSTM MIRQSTL MIRQENH MIRQENM MIRQENL ADCGO TEMPADC IRMSH IRMSM IRMSL VRMSH VRMSM VRMSL PSW TH2 Address 0xFF 0xFE 0xFD 0xFC 0xFB 0xFA 0xF9 0xF8 0xF7 0xF6 0xF5 0xF4 0xF3 0xF0 0xEF 0xEE 0xED 0xEC 0xEB 0xEA 0xEA 0xE9 0xE9 0xE8 0xE8 0xE7 0xE6 0xE5 0xE4 0xE3 0xE2 0xE1 0xE0 0xDF 0xDE 0xDD 0xDC 0xDB 0xDA 0xD9 0xD8 0xD7 0xD6 0xD5 0xD4 0xD3 0xD2 0xD1 0xD0 0xCD Details Table 16 Table 24 Table 23 Table 22 Table 21 Table 52 Table 49 Table 17 Table 124 Table 123 Table 18 Table 19 Table 50 Table 56 Table 53 Table 142 Table 91 Table 20 Table 141 Table 149 Table 153 Table 148 Table 152 Table 147 Table 151 Table 30 Table 30 Table 30 Table 30 Table 30 Table 30 Table 140 Table 56 Table 54 Table 42 Table 41 Table 40 Table 45 Table 44 Table 43 Table 51 Table 55 Table 30 Table 30 Table 30 Table 30 Table 30 Table 30 Table 57 Table 110
ADE5166/ADE5169/ADE5566/ADE5569
Mnemonic TL2 RCAP2H RCAP2L T2CON EADRH EADRL POWCON KYREG WDCON STCON EDATA PROTKY FLSHKY ECON IP SPH PINMAP2 PINMAP1 PINMAP0 LCDCONY CFG LCDDAT LCDPTR IEIP2 IE DPCON RTCDAT RTCPTR TIMECON2 TIMECON P2 EPCFG SBAUDT SBAUDF LCDCONX SPI2CRx SPI2CTx SBUF SCON LCDSEGE LCDCLK LCDCON MDATH MDATM MDATL MADDPT P1 TH1 TH0 TL1
Rev. PrB | Page 19 of 148
Address 0xCC 0xCB 0xCA 0xC8 0xC7 0xC6 0xC5 0xC1 0xC0 0xBF 0xBC 0xBB 0xBA 0xB9 0xB8 0xB7 0xB4 0xB3 0xB2 0xB1 0xAF 0xAE 0xAC 0xA9 0xA8 0xA7 0xA4 0xA3 0xA2 0xA1 0xA0 0x9F 0x9E 0x9D 0x9C 0x9B 0x9A 0x99 0x98 0x97 0x96 0x95 0x94 0x93 0x92 0x91 0x90 0x8D 0x8C 0x8B
Details Table 111 Table 112 Table 113 Table 105 Table 100 Table 99 Table 25 Table 116 Table 78 Table 64 Table 98 Table 97 Table 96 Table 95 Table 72 Table 63 Table 158 Table 157 Table 156 Table 84 Table 65 Table 90 Table 89 Table 73 Table 71 Table 69 Table 122 Table 121 Table 120 Table 119 Table 161 Table 155 Table 136 Table 137 Table 82 Table 146 Table 145 Table 135 Table 134 Table 88 Table 85 Table 81 Table 30 Table 30 Table 30 Table 30 Table 160 Table 108 Table 106 Table 109
ADE5166/ADE5169/ADE5566/ADE5569
Mnemonic TL0 TMOD TCON PCON Address 0x8A 0x89 0x88 0x87 Details Table 107 Table 103 Table 104 Table 58 Mnemonic DPH DPL SP P0
Preliminary Technical Data
Address 0x83 0x82 0x81 0x80 Details Table 60 Table 59 Table 62 Table 159
Rev. PrB | Page 20 of 148
Preliminary Technical Data POWER MANAGEMENT
The ADE5166/ADE5169/ADE5566/ADE5569 have elaborate power management circuitry that manages the regular power supply to battery switchover and power supply failures. Table 15. Power Management SFRs
SFR Address 0xEC 0xF5 0xF8 0xFF 0xF4 0xC5 0xFB 0xFC 0xFD 0xFE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic IPSME BATPR IPSMF INTPR PERIPH POWCON SCRATCH1 SCRATCH2 SCRATCH3 SCRATCH4
ADE5166/ADE5169/ADE5566/ADE5569
The power management functionalities can be accessed directly through the 8052 SFRs (see Table 15).
Description Power management interrupt enable. See Table 20. Battery switchover configuration. See Table 18. Power management interrupt flag. See Table 17. Interrupt pins configuration. See Table 16. Peripheral configuration. See Table 19. Power control. See Table 25. Scratch Pad 1. See Table 21. Scratch Pad 2. See Table 22. Scratch Pad 3. See Table 23. Scratch Pad 4. See Table 24.
POWER MANAGEMENT REGISTER DETAILS
Table 16. Interrupt Pins Configuration SFR (INTPR, 0xFF)
Bit 7 6 to 5 Mnemonic RTCCAL FSEL[1:0] Default 0 00 Description Controls RTC calibration output. When set, the RTC calibration frequency selected by FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin. Sets RTC calibration output frequency and calibration window. FSEL[1:0] Result (Calibration window, frequency) 00 30.5 sec, 1 Hz 01 30.5 sec, 512 Hz 10 0.244 sec, 500 Hz 11 0.244 sec, 16.384 kHz Controls the function of INT1. INT1PRG[2:0] X00 X01 01X 11X 0 INT0PRG 0 INT0PRG 0 1 Result GPIO enabled BCTRL enabled INT1 input disabled INT1 input enabled Result INT0 input disabled INT0 input enabled
4 3 to 1
Reserved INT1PRG[2:0]
N/A 000
Controls the function of INT0.
Writing to the Interrupt Pins Configuration SFR (INTPR, 0xFF)
To protect the RTC from runaway code, a key must be written to the key SFR (KYREG, 0xC1) to obtain write access to INTPR. KYREG (see Table 116) should be set to 0xEA to unlock this SFR and reset to zero after a timekeeping register is written to. The RTC registers can be written using the following 8052 assembly code:
MOV MOV KYREG, #0EAh INTPR, #080h
Rev. PrB | Page 21 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Table 17. Power Management Interrupt Flag SFR (IPSMF, 0xF8)
Bit 7 6 5 4 3 2 1 0 Address 0xFF 0xFE 0xFD 0xFC 0xFB 0xFA 0xF9 0xF8 Mnemonic FPSR FPSM FSAG Reserved FVADC FBAT FBSO FVDCIN Default 0 0 0 0 0 0 0 0
Preliminary Technical Data
Description Power supply restored interrupt flag. Set when the VDD power supply has been restored. This occurs when the source of VSWOUT changes from VBAT to VDD. PSM interrupt flag. Set when an enabled PSM interrupt condition occurs. Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs. This bit must be kept cleared for proper operation. VDCIN monitor interrupt flag. Set when VDCIN changes by VDCIN_DIFF or when VDCIN measurement is ready. VBAT monitor interrupt flag. Set when VBAT falls below BATVTH or when VBAT measurement is ready. Battery switchover interrupt flag. Set when VSWOUT switches from VDD to VBAT. VDCIN monitor interrupt flag. Set when VDCIN falls below 1.2 V.
Table 18. Battery Switchover Configuration SFR (BATPR, 0xF5)
Bit 7 to 2 1 to 0 Mnemonic Reserved BATPRG[1:0] Default 0 0 Description These bits must be kept to 0 for proper operation. Control bits for battery switchover. BATPRG[1:0] Result 00 Battery switchover enabled on low VDD 01 Battery switchover enabled on low VDD and low VDCIN 1X Battery switchover disabled
Table 19. Peripheral Configuration SFR (PERIPH, 0xF4)
Bit 7 6 5 4 3 2 1 to 0 Mnemonic RXFLAG VSWSOURCE VDD_OK PLL_FLT REF_BAT_EN Reserved RXPROG[1:0] Default 0 1 1 0 0 0 0 Description If set, indicates that an Rx edge event triggered wake-up from PSM2. Indicates the power supply that is internally connected to VSWOUT (0 VSWOUT = VBAT, 1 VSWOUT = VDD). If set, indicates that VDD power supply is ready for operation. If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (see Table 51) in the start ADC measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear the PLL_FLT bit. Set this bit to enable internal voltage reference in PSM2 mode. This bit should be set if LCD is on in PSM2 mode. This bit should be kept to 0. Controls the function of the P1.0/RxD pin. RXPROG[1:0] Result 00 GPIO 01 RxD with wake-up disabled 11 RxD with wake-up enabled
Table 20. Power Management Interrupt Enable SFR (IPSME, 0xEC)
Bit 7 6 5 4 3 2 1 0 Mnemonic EPSR Reserved ESAG Reserved EVADC EBAT EBSO EVDCIN Default 0 0 0 0 0 0 0 0 Description Enables a PSM interrupt when the power supply restored flag (FPSR) is set. Reserved. Enables a PSM interrupt when the voltage SAG flag (FSAG) is set. This bit must be kept cleared for proper operation. Enables a PSM interrupt when the VADC monitor flag (FVADC) is set. Enables a PSM interrupt when the VBAT monitor flag (FBAT) is set. Enables a PSM interrupt when the battery switchover flag (FBSO) is set. Enables a PSM interrupt when the VDCIN monitor flag (FVDCIN) is set.
Table 21. Scratch Pad 1 SFR (SCRATCH1, 0xFB)
Bit 7 to 0 Mnemonic SCRATCH1 Default 0 Description Value can be written/read in this register. This value is maintained in all the power saving modes.
Rev. PrB | Page 22 of 148
Preliminary Technical Data
Table 22. Scratch Pad 2 SFR (SCRATCH2, 0xFC)
Bit 7 to 0 Mnemonic SCRATCH2 Default 0
ADE5166/ADE5169/ADE5566/ADE5569
Description Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 23. Scratch Pad 3 SFR (SCRATCH3, 0xFD)
Bit 7 to 0 Mnemonic SCRATCH3 Default 0 Description Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 24. Scratch Pad 4 SFR (SCRATCH4, 0xFE)
Bit 7 to 0 Mnemonic SCRATCH4 Default 0 Description Value can be written/read in this register. This value is maintained in all the power saving modes.
Clearing the Scratch Pad Registers (SCRATCH1, 0xFB to SCRATCH4, 0xFE)
Note that these scratch pad registers are only cleared when the part loses VDD and VBAT. They are not cleared by software, watchdog, or PLL reset and, therefore, need to be set correctly in these situations. Table 25. Power Control SFR (POWCON, 0xC5)
Bit 7 6 5 4 3 2 to 0 Mnemonic Reserved METER_OFF Reserved COREOFF Reserved CD[2:0] Default 1 0 0 0 0 010 Description Reserved. Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering functions are not needed in PSM0. This bit should be kept at 0 for proper operation. Set this bit to shut down the core and enter PSM2 if in the PSM1 operating mode. Reserved. Controls the core clock frequency, fCORE. fCORE = 4.096 MHz/2CD. CD[2:0] Result (fCORE in MHz) 000 4.096 001 2.048 010 1.024 011 0.512 100 0.256 101 0.128 110 0.064 111 0.032
Writing to the Power Control SFR (POWCON, 0xC5)
Writing data to the POWCON SFR involves writing 0xA7 into the key SFR (KYREG, 0xC1), which is described in Table 116, followed by a write to the POWCON SFR. For example:
MOV KYREG,#0A7h MOV POWCON,#10h ;Write KYREG to 0xA7 to get write access to the POWCON SFR ;Shutdown the core
Rev. PrB | Page 23 of 148
ADE5166/ADE5169/ADE5566/ADE5569
POWER SUPPLY ARCHITECTURE
Each ADE5166/ADE5169/ADE5566/ADE5569 has two power supply inputs, VDD and VBAT, and require only a single 3.3 V power supply at VDD for full operation. A battery backup, or secondary power supply, with a maximum of 3.7 V can be connected to the VBAT input. Internally, the ADE5166/ADE5169/ADE5566/ ADE5569 connect VDD or VBAT to VSWOUT, which is used to derive power for the ADE5166/ADE5169/ADE5566/ADE5569 circuitry. The VSWOUT output pin reflects the voltage at the internal power supply (VSWOUT) and has a maximum output current of 6 mA. This pin can also be used to power a limited number of peripheral components. The 2.5 V analog supply (VINTA) and the 2.5 V supply for the core logic (VINTD) are derived by on-chip linear regulators from VSWOUT. Figure 10 shows the power supply architecture of ADE5166/ADE5169/ADE5566/ADE5569. The ADE5166/ADE5169/ADE5566/ADE5569 provide automatic battery switchover between VDD and VBAT based on the voltage level detected at VDD or VDCIN. Additionally, the BCTRL input can be used to trigger a battery switchover. The conditions for switching VSWOUT from VDD to VBAT and back to VDD are described in the Battery Switchover section. VDCIN is an input pin that can be connected to a 0 V to 3.3 V dc signal. This input is intended for power supply supervisory purposes and does not provide power to the ADE5166/ADE5169/ADE5566/ ADE5569 circuitry (see the Battery Switchover section).
VDCIN VDD VBAT VSWOUT
Preliminary Technical Data
The battery switchover functionality provided by the ADE5166/ ADE5169/ADE5566/ADE5569 allows a seamless transition from VDD to VBAT. An automatic battery switchover option ensures a stable power supply to the ADE5166/ADE5169/ ADE5566/ADE5569, as long as the external battery voltage is above 2.75 V. It allows continuous code execution even while the internal power supply is switching from VDD to VBAT and back. Note that the energy metering ADCs are not available when VBAT is being used for VSWOUT. Power supply management (PSM) interrupts can be enabled to indicate when battery switchover occurs and when the VDD power supply is restored (see the Power Supply Management Interrupt (PSM) section.)
VDD to VBAT
The following three events switch the internal power supply (VSWOUT) from VDD to VBAT: * VDCIN < 1.2 V. When VDCIN falls below 1.2 V, VSWOUT switches from VDD to VBAT. This event is enabled when the BATPRG[1:0] bits in the battery switchover configuration SFR (BATPR, 0xF5) = 0b01. Setting these bits disables switchover based on VDCIN. Battery switchover on low VDCIN is disabled by default. VDD < 2.75 V. When VDD falls below 2.75 V, VSWOUT switches from VDD to VBAT. This event is enabled when BATPRG[1:0] in the BATPR SRF are cleared. Falling edge on BCTRL. When the battery control pin, BCTRL, goes low, VSWOUT switches from VDD to VBAT. This external switchover signal can trigger a switchover to VBAT at any time. Setting Bits INT1PRG[4:2] to 0bx01 in the interrupt pins configuration SFR (INTPR, 0xFF) enables the battery control pin (see Table 16).
*
*
LDO VINTD MCU
ADC
BCTRL
POWER SUPPLY MANAGEMENT
VSW LDO ADC
VINTA
ADE
SPI/I2C SCRATCHPAD LCD RTC UART TEMPERATURE ADC 3.3V 2.5V
07411-011
Switching from VBAT to VDD
To switch VSWOUT from VBAT to VDD, all of the following events that are enabled to force battery switchover must be false: * VDCIN < 1.2 V and VDD < 2.75 V enabled. If the low VDCIN condition is enabled, VSWOUT switches to VDD after VDCIN remains above 1.2 V and VDD remains above 2.75 V. VDD < 2.75 V enabled. VSWOUT switches back to VDD after VDD remains above 2.75 V. BCTRL enabled. VSWOUT switches back to VDD after BCTRL is high, and the first or second bullet point is satisfied.
Figure 10. Power Supply Architecture
BATTERY SWITCHOVER
The ADE5166/ADE5169/ADE5566/ADE5569 monitor VDD, VBAT, and VDCIN. Automatic battery switchover from VDD to VBAT can be configured based on the status of VDD, VDCIN, or the BCTRL pin. Battery switchover is enabled by default. Setting Bit 1 in the battery switchover configuration SFR (BATPR, 0xF5) disables battery switchover so that VDD is always connected to VSWOUT (see Table 18). The source of VSWOUT is indicated by Bit 6 in the peripheral configuration SFR (PERIPH, 0xF4), which is described in Table 19. Bit 6 is set when VSWOUT is connected to VDD and cleared when VSWOUT is connected to VBAT. * *
Rev. PrB | Page 24 of 148
Preliminary Technical Data
POWER SUPPLY MANAGEMENT INTERRUPT (PSM)
The power supply management interrupt (PSM) alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the interrupt enable and Priority 2 SFR (IEIP2, 0xA9) enables the PSM interrupt (see Table 73).
EPSR FPSR ESAG FSAG EVADC FVADC EBAT FBAT EBSO FBSO EVDCIN FVDCIN FPSM EPSM
ADE5166/ADE5169/ADE5566/ADE5569
The power management interrupt enable SFR (IPSME, 0xEC) controls the events that result in a PSM interrupt (see Table 20). Figure 11 is a diagram illustrating how the PSM interrupt vector is shared among the PSM interrupt sources. The PSM interrupt flags are latched and must be cleared by writing to the IPSMF flag register (see Table 17).
TRUE?
PENDING PSM INTERRUPT
IPSME ADDR. 0xEC
EPSR
RESERVED
ESAG
RESERVED
EVADC
EBAT
EBSO
EVDCIN
IPSMF ADDR. 0xF8
FPSR
FPSM
FSAG
RESERVED
FVADC
FBAT
FBSO
FVDCIN
IEIP2 ADDR. 0xA9
PS2
PTI
ES2
PSI
EADE
ETI
EPSM
ESI
07411-012
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN
Figure 11. PSM Interrupt Sources
Rev. PrB | Page 25 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Battery Switchover and Power Supply Restored PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 can be configured to generate a PSM interrupt when the source of VSWOUT changes from VDD to VBAT, indicating battery switchover. Setting the EBSO bit in the power management interrupt enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt (see Table 20). The ADE5166/ADE5169/ADE5566/ADE5569 can also be configured to generate an interrupt when the source of VSWOUT changes from VBAT to VDD, indicating that the VDD power supply has been restored. Setting the EPSR bit in the power management interrupt enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. The flags in the IPSMF SFR for these interrupts, FBSO and FPSR, are set regardless of whether the respective enable bits have been set. The battery switchover and power supply restore event flags, FBSO and FPSR, are latched. These events must be cleared by writing a 0 to these bits. Bit 6 in the peripheral configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the source of VSWOUT. The bit is set when VSWOUT is connected to VDD and cleared when VSWOUT is connected to VBAT.
Preliminary Technical Data
VBAT Monitor PSM Interrupt
The VBAT voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in VBAT. The FBAT bit is set when the battery level is lower than the threshold set in the battery detection threshold SFR (BATVTH, 0xFA), described in Table 52, or when a new measurement is ready in the battery ADC value SFR (BATADC, 0xDF), described in Table 54. See the Battery Measurement section for more information. Setting the EBAT bit in the power management interrupt enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt.
VDCIN Monitor PSM Interrupt
The VDCIN voltage is monitored by a comparator. The FVDCIN bit in the power management interrupt flag SFR (IPSMF, 0xF8) is set when the VDCIN input level is lower than 1.2 V. Setting the EVDCIN bit in the IPSME SFR enables this event to generate a PSM interrupt. This event, which is associated with the SAG monitoring, can be used to detect a power supply (VDD) being compromised and to trigger further actions prior to deciding a switch of VDD to VBAT.
SAG Monitor PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 energy measurement DSP monitors the ac voltage input at the VP and VN input pins. The SAGLVL register is used to set the threshold for a line voltage SAG event. The FSAG bit in the power management interrupt flag SFR (IPSMF, 0xF8) is set if the line voltage stays below the level set in the SAGLVL register for the number of line cycles set in the SAGCYC register. See the Line Voltage SAG Detection section for more information. Setting the ESAG bit in the power management interrupt enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt.
VDCIN ADC PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 can be configured to generate a PSM interrupt when VDCIN changes magnitude by more than a configurable threshold. This threshold is set in the temperature and supply delta SFR (DIFFPROG, 0xF3), which is described in Table 50. See the External Voltage Measurement section for more information. Setting the EVDCIN bit in the power management interrupt enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. The VDCIN voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in VDCIN. Conversions can also be initiated by writing to the start ADC measurement SFR (ADCGO, 0xD8) described in Table 51. The FVDCIN flag indicates when a VDCIN measurement is ready. See the External Voltage Measurement section for details on how VDCIN is measured.
Rev. PrB | Page 26 of 148
Preliminary Technical Data
USING THE POWER SUPPLY FEATURES
In an energy meter application, the 3.3 V power supply (VDD) is typically generated from the ac line voltage and regulated to 3.3 V by a voltage regulator IC. The preregulated dc voltage, typically 5 V to 12 V, can be connected to VDCIN through a resistor divider. A 3.6 V battery can be connected to VBAT. Figure 12 shows how the ADE5166/ADE5169/ADE5566/ ADE5569 power supply inputs are set up in this application. Figure 13 shows the sequence of events that occurs if the main power supply generated by the PSU starts to fail in the power meter application shown in Figure 12. The SAG detection can provide the earliest warning of a potential problem on VDD.
ADE5166/ADE5169/ADE5566/ADE5569
When a SAG event occurs, user code can be configured to back up data and prepare for battery switchover if desired. The relative spacing of these interrupts depends on the design of the power supply. Figure 14 shows the sequence of events that occurs if the main power supply starts to fail in the power meter application shown in Figure 12, with battery switchover on low VDCIN or low VDD enabled. Finally, the transition between VDD and VBAT and the different power supply modes (see the Operating Modes section) are represented in Figure 15 and Figure 16.
(240V, 220V, 110V TYPICAL) AC INPUT
BCTRL 45 VP
49
VN
50
SAG DETECTION
5V TO 12V DC
VDCIN
64
VOLTAGE SUPERVISORY
VOLTAGE SUPERVISORY 3.3V REGULATOR VDD
60
POWER SUPPLY MANAGEMENT
IPSMF SFR (ADDR. 0xF8)
PSU
VSW VSWOUT 61
07411-013
VBAT 58
Figure 12. Power Supply Management for Energy Meter Application
VP - VN SAG LEVEL TRIP POINT SAGCYC = 1
VDCIN 1.2V
VDD 2.75V
t1
t2
SAG EVENT (FSAG = 1) VDCIN EVENT (FVDCIN = 1) IF SWITCHOVER ON LOW VDD IS ENABLED, AUTOMATIC BATTERY SWITCHOVER VSWOUT CONNECTED TO VBAT
BSO EVENT (FBSO = 1)
Figure 13. Power Supply Management Interrupts and Battery Switchover with Only VDD Enabled for Battery Switchover
Rev. PrB | Page 27 of 148
07411-014
ADE5166/ADE5169/ADE5566/ADE5569
Table 26. Power Supply Event Timing Operating Modes
Parameter t1 t2 t3 t4 Time 10 ns min 10 ns min 30 ms typ 130 ms typ
Preliminary Technical Data
Description Time between when VDCIN goes below 1.2 V and when FVDCIN is raised. Time between when VDD falls below 2.75 V and when battery switchover occurs. Time between when VDCIN falls below 1.2 V and when battery switchover occurs if VDCIN is enabled to cause battery switchover. Time between when power supply restore conditions are met (VDCIN above 1.2 V and VDD above 2.75 V if BATPR[1:0] = 0b01 or VDD above 2.75 V if BATPR[1:0] = 0b00) and when VSWOUT switches to VDD.
VP - VN SAG LEVEL TRIP POINT SAGCYC = 1
VDCIN 1.2V
t3
VDD 2.75V
t1
SAG EVENT (FSAG = 1)
VDCIN EVENT (FVDCIN = 1)
IF SWITCHOVER ON LOW VDCIN IS ENABLED, AUTOMATIC BATTERY SWITCHOVER VSWOUT CONNECTED TO VBAT
BSO EVENT (FBSO = 1)
Figure 14. Power Supply Management Interrupts and Battery Switchover with VDD or VDCIN Enabled for Battery Switchover
VP - VN
SAG LEVEL TRIP POINT
VDCIN 1.2V
SAG EVENT
VDCIN EVENT
VDCIN EVENT
30ms MIN. VBAT VDD 2.75V
130ms MIN.
VSW BATTERY SWITCH ENABLED ON LOW VDCIN VSW BATTERY SWITCH ENABLED ON LOW VDD
PSM0 PSM1 OR PSM2
PSM0
PSM0
PSM0
PSM1 OR PSM2
Figure 15. Power Supply Management Transitions Between Modes
Rev. PrB | Page 28 of 148
07411-016
07411-015
Preliminary Technical Data OPERATING MODES
PSM0 (NORMAL MODE)
In PSM0, normal operating mode, VSWOUT is connected to VDD. All of the analog circuitry and digital circuitry powered by VINTD and VINTA are enabled by default. In normal mode, the default clock frequency, fCORE, established during a power-on reset or software reset, is 1.024 MHz.
ADE5166/ADE5169/ADE5566/ADE5569
PSM2 (SLEEP MODE)
PSM2 is a low power consumption sleep mode for use in battery operation. In this mode, VSWOUT is connected to VBAT. All of the 2.5 V digital and analog circuitry powered through VINTA and VINTD are disabled, including the MCU core, resulting in the following: * * The RAM in the MCU is no longer valid. The program counter for the 8052, also held in volatile memory, becomes invalid when the 2.5 V supply is shut down. Therefore, the program does not resume from where it left off but always starts from the power-on reset vector when the ADE5166/ADE5169/ADE5566/ADE5569 exit PSM2.
PSM1 (BATTERY MODE)
In PSM1, battery mode, VSWOUT is connected to VBAT. In this operating mode, the 8052 core and all of the digital circuitry are enabled by default. The analog circuitry for the ADE energy metering DSP powered by VINTA is disabled. This analog circuitry automatically restarts, and the switch to the VDD power supply occurs when the VDD supply is above 2.75 V and when the PWRDN bit in the MODE1 register (0x0B) is cleared (see Table 32). The default fCORE for PSM1, established during a power-on reset or software reset, is 1.024 MHz.
The 3.3 V peripherals (temperature ADC, VDCIN ADC, RTC, and LCD) are active in PSM2. They can be enabled or disabled to reduce power consumption and are configured for PSM2 operation when the MCU core is active (see Table 28 for more information about the individual peripherals and their PSM2 configuration). The ADE5166/ADE5169/ADE5566/ADE5569 remain in PSM2 until an event occurs to wake them up. In PSM2, the ADE5166/ADE5169/ADE5566/ADE5569 provide four scratch pad RAM SFRs that are maintained during this mode. These SFRs can be used to save data from PSM0 or PSM1 when entering PSM2 (see Table 21 to Table 24). In PSM2, the ADE5166/ADE5169/ADE5566/ADE5569 maintain some SFRs (see Table 27). The SFRs that are not listed in this table should be restored when the part enters PSM0 or PSM1 from PSM2.
Table 27. SFR Maintained in PSM2
I/O Configuration Interrupt Pins Configuration SFR (INTPR, 0xFF), see Table 16 Peripheral Configuration SFR (PERIPH, 0xF4), see Table 19 Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2), see Table 156 Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3), see Table 157 Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4), see Table 158 Scratch Pad 1 SFR (SCRATCH1, 0xFB), see Table 21 Scratch Pad 2 SFR (SCRATCH2, 0xFC), see Table 22 Scratch Pad 3 SFR (SCRATCH3, 0xFD), see Table 23 Scratch Pad 4 SFR (SCRATCH4, 0xFE), see Table 24 Power Supply Management Battery Detection Threshold SFR (BATVTH, 0xFA), see Table 52 Battery Switchover Configuration SFR (BATPR, 0xF5), see Table 18 Battery ADC Value SFR (BATADC, 0xDF), see Table 54 Peripheral ADC Strobe Period SFR (STRBPER, 0xF9), see Table 49 Temperature and Supply Delta SFR (DIFFPROG, 0xF3), see Table 50 VDCIN ADC Value SFR (VDCINADC, 0xEF), see Table 53 Temperature ADC Value SFR (TEMPADC, 0xD7), see Table 55 RTC Peripherals RTC Nominal Compensation SFR (RTCCOMP, 0xF6), see Table 123 RTC Temperature Compensation SFR (TEMPCAL, 0xF7), see Table 124 RTC Configuration SFR (TIMECON, 0xA1), see Table 119 RTC Configuration 2 SFR (TIMECON2, 0xA2), see Table 120 All indirectly accessible register defined in the RTC register list. See Table 126 LCD Peripherals LCD Segment Enable 2 SFR (LCDSEGE2, 0xED), see Table 91 LCD Configuration Y SFR (LCDCONY, 0xB1), see Table 84 LCD Configuration X SFR (LCDCONX, 0x9C), see Table 82 LCD Configuration SFR (LCDCON, 0x95), see Table 81 LCD Clock SFR (LCDCLK, 0x96), see Table 85 LCD Segment Enable SFR (LCDSEGE, 0x97) see Table 88 LCD Pointer SFR (LCDPTR, 0xAC), see Table 89 LCD Data SFR (LCDDAT, 0xAE), see Table 90
Rev. PrB | Page 29 of 148
ADE5166/ADE5169/ADE5566/ADE5569
3.3 V PERIPHERALS AND WAKE-UP EVENTS
Some of the 3.3 V peripherals are capable of waking the ADE5166/ADE5169/ADE5566/ADE5569 from PSM2. The events that can cause the ADE5166/ADE5169/ADE5566/ ADE5569 to wake up from PSM2 are listed in the Wake-Up Table 28. 3.3 V Peripherals and Wake-Up Events
3.3 V Peripheral Temperature ADC WakeUp Event T Wake-Up Enable Bits Maskable Interrupt Vector ITADC
Preliminary Technical Data
Event column in Table 28. The interrupt flag associated with these events must be cleared prior to executing instructions that put the ADE5166/ADE5169/ADE5566/ADE5569 in PSM2 mode after wake-up.
Flag
VDCIN ADC
V
Maskable
FVADC
IPSM
Power Supply Management
PSR
Nonmaskable
PSR
IPSM
RTC
Interval
Maskable
ITFLAG
IRTC
Alarm
Maskable
Alarm
IRTC
I/O Ports1
INT0
INT0PRG = 1
IE0
INT1
INT1PRG[2:0] = 11x
IE1
Rx Edge
RXPROG[1:0] = 11 Nonmaskable
PERIPH[7] (RXFG)
External Reset LCD Scratch Pad
1
RESET
Comments The temperature ADC can wake up the ADE5166/ADE5169/ ADE5566/ADE5569 if the ITADC flag is set. A pending interrupt is generated according to the description in the Temperature Measurement section. This wake-up event can be disabled by disabling temperature measurements in the temperature and supply delta SFR (DIFFPROG, 0xF3) in PSM2. The temperature interrupt needs to be serviced and acknowledged prior to entering PSM2 mode. The VDCIN measurement can wake up the ADE5166/ADE5169/ ADE5566/ADE5569. FVADC is set according to the description in the External Voltage Measurement section. This wake-up event can be disabled by clearing EVADC in the power management interrupt enable SFR (IPSME, 0xEC); see Table 20. The FVADC flag needs to be cleared prior to entering PSM2 mode. The ADE5166/ADE5169/ADE5566/ADE5569 wake up if the power supply is restored (if VSWOUT switches to be connected to VDD). The VSWSOURCE flag, Bit 6 of the peripheral configuration SFR (PERIPH, 0xF4), is set to indicate that VSWOUT is connected to VDD. The ADE5166/ADE5169/ADE5566/ADE5569 wake up after the programmable time interval has elapsed. The RTC interrupt needs to be serviced and acknowledged prior to entering PSM2 mode. An alarm can be set to wake the ADE5166/ADE5169/ADE5566/ ADE5569 after the desired amount of time. The RTC alarm is enabled by setting the corresponding ALxx_EN bits in the RTC Configuration 2 SFR (TIMECON2, 0xA2). The RTC interrupt needs to be serviced and acknowledged prior to entering PSM2 mode. The edge of the interrupt is selected by Bit IT0 in the TCON register. The IE0 flag bit in the TCON register is not affected. The Interrupt 0 interrupt needs to be serviced and acknowledged prior to entering PSM2 mode. The edge of the interrupt is selected by Bit IT1 in the TCON register. The IE1 flag bit in the TCON register is not affected. The Interrupt 1 interrupt needs to be serviced and acknowledged prior to entering PSM2 mode. An Rx edge event occurs if a rising or falling edge is detected on the Rx line. The UART RxD flag needs to be cleared prior to entering PSM2 mode. If the RESET pin is brought low while the ADE5166/ADE5169/ ADE5566/ADE5569 is in PSM2, it wakes up to PSM1. The LCD can be enabled/disabled in PSM2. The LCD data memory remains intact. The four SCRATCHx registers remain intact in PSM2.
All I/O pins are treated as inputs. The weak pull-up on each I/O pin can be disabled individually in the Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2), Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3), and Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4) to decrease current consumption. The interrupts can be enabled/disabled.
Rev. PrB | Page 30 of 148
Preliminary Technical Data
TRANSITIONING BETWEEN OPERATING MODES
The operating mode of the ADE5166/ADE5169/ADE5566/ ADE5569 is determined by the power supply connected to VSWOUT. Therefore, changes in the power supply, such as when VSWOUT switches from VDD to VBAT or when VSWOUT switches to VDD, alter the operating mode. This section describes events that change the operating mode.
ADE5166/ADE5169/ADE5566/ADE5569
Automatic Switch to VDD (PSM1 to PSM0)
If the conditions to switch VSWOUT from VBAT to VDD occur (see the Battery Switchover section), the operating mode switches to PSM0. When this switch occurs, the analog circuitry used in the ADE energy measurement DSP automatically restarts. Note that code execution continues normally. A software reset can be performed to start PSM0 code execution at the power-on reset vector.
Automatic Battery Switchover (PSM0 to PSM1)
If any of the enabled battery switchover events occur (see the Battery Switchover section), VSWOUT switches to VBAT. This switchover results in a transition from PSM0 to PSM1 operating mode. When battery switchover occurs, the analog circuitry used in the ADE energy measurement DSP is disabled. To reduce power consumption, the user code can initiate a transition to PSM2.
USING THE POWER MANAGEMENT FEATURES
Because program flow is different for each operating mode, the status of VSWOUT must be known at all times. The VSWSOURCE bit in the peripheral configuration SFR (PERIPH, 0xF4) indicates what VSWOUT is connected to (see Table 19). This bit can be used to control program flow on wake-up. Because code execution always starts at the power-on reset vector, Bit 6 of the PERIPH SRF can be tested to determine which power supply is being used and to branch to normal code execution or to wake up event code execution. Power supply events can also occur when the MCU core is active. To be aware of the events that change what VSWOUT is connected to, use the following guidelines: * * Enable the battery switchover interrupt (EBSO) if VSWOUT = VDD at power-up. Enable the power supply restored interrupt (EPSR) if VSWOUT = VBAT at power-up.
Entering Sleep Mode (PSM1 to PSM2)
To reduce power consumption when VSWOUT is connected to VBAT, user code can initiate sleep mode, PSM2, by setting Bit 4 in the power control SFR (POWCON, 0xC5) to shut down the MCU core. Events capable of waking the MCU can be enabled (see the 3.3 V Peripherals and Wake-Up Events section).
Servicing Wake-Up Events (PSM2 to PSM1)
The ADE5166/ADE5169/ADE5566/ADE5569 may need to wake up from PSM2 to service wake-up events (see the 3.3 V Peripherals and Wake-Up Events section). PSM1 code execution begins at the power-on reset vector. After servicing the wake-up event, the ADE5166/ADE5169/ADE5566/ ADE5569 can return to PSM2 by setting Bit 4 in the power control SFR (POWCON, 0xC5) to shut down the MCU core.
An early warning that battery switchover is about to occur is provided by SAG detection and possibly low VDCIN detection (see the Battery Switchover section). For a user-controlled battery switchover, enable automatic battery switchover on low VDD only. Then, enable the low VDCIN event to generate the PSM interrupt. When a low VDCIN event occurs, start data backup. Upon completion of the data backup, enable battery switchover on low VDCIN. Battery switchover occurs 30 ms later.
Automatic Switch to VDD (PSM2 to PSM0)
If the conditions to switch VSWOUT from VBAT to VDD occur (see the Battery Switchover section), the operating mode switches to PSM0. When this switch occurs, the MCU core and the analog circuitry used in the ADE energy measurement DSP automatically restart. PSM0 code execution begins at the power-on reset vector.
Rev. PrB | Page 31 of 148
ADE5166/ADE5169/ADE5566/ADE5569
POWER SUPPLY RESTORED
Preliminary Technical Data
PSM0
NORMAL MODE VSWOUT CONNECTED TO VDD
AUTOMATIC BATTERY SWITCHOVER
PSM1
BATTERY MODE VSWOUT CONNECTED TO VBAT
POWER SUPPLY RESTORED
WAKE-UP EVENT USER CODE DIRECTS MCU TO SHUT DOWN CORE AFTER SERVICING WAKE-UP EVENT
PSM2
07411-017
SLEEP MODE VSWOUT CONNECTED TO VBAT
Figure 16. Transitioning Between Operating Modes
Rev. PrB | Page 32 of 148
Preliminary Technical Data ENERGY MEASUREMENT
The ADE5166/ADE5169/ADE5566/ADE5569 offer a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access through SFRs for time sensitive information and indirect access through address and data SFR registers for the majority of energy measurements. The Irms, Vrms, interrupts, and waveform registers are readily available through SFRs, as shown in Table 30. Other energy measurement information is mapped to a page of memory that is accessed indirectly through the MADDPT, MDATL, MDATM, and MDATH SFRs. The address and data registers act as pointers to the energy measurement internal registers.
ADE5166/ADE5169/ADE5566/ADE5569
energy measurement register designated by the address in the MADDPT SFR. If the internal register is 1 byte long, only the MDATL SFR content is copied to the internal register, while the MDATM SFR and MDATH SFR contents are ignored. The energy measurement core functions with an internal clock of 4.096 MHz 5 or 819.2 kHz. Because the 8052 core functions with another clock, 4.096MHz 2CD, synchronization between the two clock environments when CD = 0 or 1 is an issue. When data is written to the internal energy measurement registers, a small wait period needs to be implemented before another read or write to these registers can take place. Sample code to write 0x0155 to the 2-byte SAGLVL register located at 0x14 in the energy measurement memory space is as follows:
MOV MOV MOV MOV DJNZ MDATM,#01h MDATL,#55h MADDPT,#SAGLVL_W (Address 0x94) A,#05h ACC,$ ;Next write or read to energy measurement SFR can be done after this.
ACCESS TO ENERGY MEASUREMENT SFRs
Access to the energy measurement SFRs is achieved by reading or writing to the SFR addresses detailed in Table 30. The internal data for the MIRQx SFRs are latched byte by byte into the SFR when the SFR is read. The WAV1x, WAV2x, VRMSx, and IRMSx registers are all 3-byte SFRs. The 24-bit data is latched into these SFRs when the high byte is read. Reading the low or medium byte before the high byte results in reading the data from the previous latched sample. Sample code to read the VRMSx register is as follows:
MOV MOV MOV R1, VRMSH R2, VRMSM R3, VRMSL //latches data in VRMSH, VRMSM, and VRMSL SFRs
Reading the Internal Energy Measurement Registers
When Bit 7 of energy measurement pointer address SFR (MADDPT, 0x91) is cleared, the content of the internal energy measurement register designated by the address in MADDPT is transferred to the MDATx SFRs. If the internal register is 1 byte long, only the MDATL SFR content is updated with a new value, while the MDATM SFR and MDATH SFR contents are reset to 0x00. The energy measurement core functions with an internal clock of 4.096 MHz 5 or 819.2 kHz. Because the 8052 core functions with another clock, 4.096MHz 2CD, synchronization between the two clock environments when CD = 0 or 1 is an issue. When data is read from the internal energy measurement registers, a small wait period needs to be implemented before the MDATx SFRs are transferred to another SFR. Sample code to read the peak voltage in the 2-byte VPKLVL register located at 0x16 into the data pointer is as follows:
MOV MOV DJNZ MOV MOV MADDPT,#VPKLVL_R (Address 0x16) A,#05h ACC,$ DPH,MDATM DPL,MDATL
ACCESS TO INTERNAL ENERGY MEASUREMENT REGISTERS
Access to the internal energy measurement registers is achieved by writing to the energy measurement pointer address SFR (MADDPT, 0x91). This SFR selects the energy measurement register to be accessed and determines if a read or a write is performed (see Table 29). Table 29. Energy Measurement Pointer Address SFR (MADDPT, 0x91)
Bit 7 6 to 0 Description 1 = write, 0 = read Energy measurement internal register address
Writing to the Internal Energy Measurement Registers
When Bit 7 of the energy measurement pointer address SFR (MADDPT, 0x91) is set, the content of the MDATx SFRs (MDATL, MDATM, and MDATH) is transferred to the internal
Rev. PrB | Page 33 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Table 30. Energy Measurement SFRs
Address 0x91 0x92 0x93 0x94 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7
x1, x2, x4, x8, x16 {GAIN[2:0]} PGA1 IBP PHCAL[7:0] 2
Preliminary Technical Data
R/W R/W R/W R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W R R R R R R
Mnemonic MADDPT MDATL MDATM MDATH VRMSL VRMSM VRMSH IRMSL IRMSM IRMSH MIRQENL MIRQENM MIRQENH MIRQSTL MIRQSTM MIRQSTH WAV1L WAV1M WAV1H WAV2L WAV2M WAV2H
Description Energy measurement pointer address. Energy measurement pointer data lowest significant byte. Energy measurement pointer data middle byte. Energy measurement pointer data most significant byte. Vrms measurement lowest significant byte. Vrms measurement middle byte. Vrms measurement most significant byte. Irms measurement lowest significant byte. Irms measurement middle byte. Irms measurement most significant byte. Energy measurement interrupt enable lowest significant byte. Energy measurement interrupt enable middle byte. Energy measurement interrupt enable most significant byte. Energy measurement interrupt status lowest significant byte. Energy measurement interrupt status middle byte. Energy measurement interrupt status most significant byte. Selection 1 sample lowest significant byte. Selection 1 sample middle byte. Selection 1 sample most significant byte. Selection 2 sample lowest significant byte. Selection 2 sample middle byte. Selection 2 sample most significant byte.
INTEGRATOR MULTIPLIER ADC dt HPF LPF2
IP I
WGAIN[11:0]
CF1NUM[15:0] WATTOS[15:0] VARGAIN[11:0] DFC LPF2 CF1DEN[15:0] IRMSOS[11:0] VAROS[15:0] VAGAIN[11:0] CF2NUM[15:0] CF1
x2
LPF VRMSOS[11:0] VARDIV[7:0]
DFC
CF2
VP PGA2 VN ADC HPF
x2
CF2DEN[15:0] LPF VADIV[7:0] % % % WDIV[7:0]
METERING SFRs
Figure 17. ADE5566 and ADE5569 Energy Metering Block Diagram
Rev. PrB | Page 34 of 148
07411-092
Preliminary Technical Data
IPA I IN PGA1 IBP x1, x2, x4, x8, x16 {GAIN[2:0]} PGA1 INTEGRATOR ADC HPF dt ADC MULTIPLIER LPF2
ADE5166/ADE5169/ADE5566/ADE5569
WGAIN[11:0]
HPF IBGAIN[11:0] 2
CF1NUM[15:0] WATTOS[15:0] VARGAIN[11:0] DFC LPF2 CF1DEN[15:0] IRMSOS[11:0] VAROS[15:0] VAGAIN[11:0] CF2NUM[15:0] CF1
x2
LPF VRMSOS[11:0] VARDIV[7:0]
DFC
CF2
VP PGA2 VN ADC HPF
CF2DEN[15:0]
x2
LPF
VADIV[7:0]
%
%
%
WDIV[7:0]
METERING SFRs
Figure 18. ADE5166 and ADE5169 Energy Metering Block Diagram
Rev. PrB | Page 35 of 148
07411-117
ADE5166/ADE5169/ADE5566/ADE5569
ENERGY MEASUREMENT REGISTERS
Table 31. Energy Measurement Register List
Address MADDPT[6:0] 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 Mnemonic WATTHR RWATTHR LWATTHR VARHR1 RVARHR1 LVARHR1 VAHR RVAHR LVAHR PER_FREQ MODE1 MODE2 WAVMODE NLMODE ACCMODE PHCAL ZXTOUT LINCYC SAGCYC SAGLVL IPKLVL VPKLVL IPEAK RSTIPEAK VPEAK RSTVPEAK GAIN IBGAIN2 WGAIN VARGAIN1 VAGAIN WATTOS VAROS1 IRMSOS VRMSOS WDIV VARDIV VADIV CF1NUM CF1DEN R/W R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Length (Bits) 24 24 24 24 24 24 24 24 24 16 8 8 8 8 8 8 12 16 8 16 16 16 24 24 24 24 8 12 12 12 12 16 16 12 12 8 8 8 16 16 Signed/ Unsigned S S S S S S S S S U U U U U U S Default 0 0 0 0 0 0 0 0 0 0 0x06 0x40 0 0 0 0x40 0x0FFF 0xFFFF 0xFF 0 0xFFFF 0xFFFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x003F
Preliminary Technical Data
U U U U U U U U U U S S S S S S S S U U U U U
Description Reads Wh accumulator without reset. Reads Wh accumulator with reset. Reads Wh accumulator synchronous to line cycle. Reads VARh accumulator without reset. Reads VARh accumulator with reset. Reads VARh accumulator synchronous to line cycle. Reads VAh accumulator without reset. If the VARMSCFCON bit in the MODE2 register (0x0C) is set, this register accumulates Irms. Reads VAh accumulator with reset. If the VARMSCFCON bit in the MODE2 register (0x0C) is set, this register accumulates Irms. Reads VAh accumulator synchronous to line cycle. If the VARMSCFCON bit in the MODE2 register (0x0C) is set, this register accumulates Irms. Reads line period or frequency register depending on Mode2 register. Sets basic configuration of energy measurement (see Table 32). Sets basic configuration of energy measurement (see Table 33). Sets configuration of Waveform Sample 1 and Waveform Sample 2 (see Table 34). Sets level of energy no load thresholds (see Table 35). Sets configuration of WATT, VAR accumulation, and various tamper alarms (see Table 36). Sets phase calibration register (see the Phase Compensation section). Sets timeout for zero-crossing timeout detection (see the ZeroCrossing Timeout section). Sets number of half-line cycles for LWATTHR, LVARHR, and LVAHR accumulators. Sets number of half-line cycles for SAG detection (see the Line Voltage SAG Detection section). Sets detection level for SAG detection (see the Line Voltage SAG Detection section). Sets peak detection level for current peak detection (see the Peak Detection section). Sets peak detection level for voltage peak detection (see the Peak Detection section). Reads current peak level without reset (see the Peak Detection section). Reads current peak level with reset (see the Peak Detection section). Reads voltage peak level without reset (see the Peak Detection section). Reads voltage peak level with reset (see the Peak Detection section). Sets PGA gain of analog inputs (see Table 37). Sets matching gain for IPB current input. Sets WATT gain register. Sets VAR gain register. Sets VA gain register. Sets WATT offset register. Sets VAR offset register. Sets current rms offset register. Sets voltage rms offset register. Sets WATT energy scaling register. Sets VAR energy scaling register. Sets VA energy scaling register. Sets CF1 numerator register. Sets CF1 denominator register.
Rev. PrB | Page 36 of 148
Preliminary Technical Data
Address MADDPT[6:0] 0x29 0x2A 0x2B 0x3B 0x3C 0x3D 0x3E 0x3F
1 2
ADE5166/ADE5169/ADE5566/ADE5569
Signed/ Unsigned U U U Default 0 0x003F 0 0 0x0300 0 0 0 Description Sets CF2 numerator register. Sets CF2 denominator register. Enables Zero Crossing Outputs. See Table 38. This register must be kept at its default value for proper operation. This register must be kept at its default value for proper operation. For ADE5166/ADE5169 only. Set calibration mode. This register must be kept at its default value for proper operation. This register must be kept at its default value for proper operation.
Mnemonic CF2NUM CF2DEN MODE3 Reserved Reserved CALMODE2 Reserved Reserved
R/W R/W R/W R/W
Length (Bits) 16 16 8
R/W
8
U
This function is not available in the ADE5566 and ADE5166. This function is not available in the ADE5566 and ADE5569.
ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS
Table 32. Mode 1 Register (MODE1, 0x0B)
Bit 7 6 5 4 3 2 1 0 Mnemonic SWRST DISZXLPF INTE SWAPBITS PWRDN DISCF2 DISCF1 DISHPF Default 0 0 0 0 0 1 1 0 Description Setting this bit resets all of the energy measurement registers to their default values. Setting this bit disables the zero-crossing low-pass filter. Setting this bit enables the digital integrator for use with a di/dt sensor. Setting this bit swaps CH1 ADC and CH2 ADC. Setting this bit powers down voltage and current ADCs. Setting this bit disables Frequency Output CF2. Setting this bit disables Frequency Output CF1. Setting this bit disables the HPFs in voltage and current channels.
Table 33. Mode 2 Register (MODE2, 0x0C)
Bit 7 to 6 Mnemonic CF2SEL[1:0] Default 01 Description Configuration bits for CF2 output. CF2SEL[1:0] Result 00 CF2 frequency is proportional to active power. 01 CF2 frequency is proportional to reactive power.1 1x CF2 frequency is proportional to apparent power or Irms. Configuration bits for CF1 output. CF1SEL[1:0] Result 00 CF1 frequency is proportional to active power. 01 CF1 frequency is proportional to reactive power.1 1x CF1 frequency is proportional to apparent power or Irms. Configuration bits for apparent power or Irms for CF1, CF2 outputs, and VA accumulation registers (VAHR, RVAHR, and LVAHR). Note that CF1 cannot be proportional to VA if CF2 is proportional to Irms and vice versa. VARMSCFCON Result 0 If CF1SEL[1:0] = 1x, CF1 is proportional to VA. If CF2SEL[1:0] = 1x, CF2 is proportional to VA. 1 If CF1SEL[1:0] = 1x, CF1 is proportional to Irms. If CF2SEL[1:0] = 1x, CF2 is proportional to Irms. Logic 1 enables update of rms values synchronously to Voltage ZX.
5 to 4
CF1SEL[1:0]
00
3
VARMSCFCON
0
2
ZXRMS
0
Rev. PrB | Page 37 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Bit 1 Mnemonic FREQSEL Default 0
Preliminary Technical Data
0
1
WAVEN
0
Description Configuration Bits to Select Period or Frequency Measurement for PER_FREQ Register (0x0A). FREQSEL Result 0 PER_FREQ register holds a period measurement. 1 PER_FREQ register holds a frequency measurement. When this bit is set, waveform sampling mode is enabled.
This function is not available in the ADE5566 and ADE5166.
Table 34. Waveform Mode Register (WAVMODE, 0x0D)
Bit 7 to 5 Mnemonic WAV2SEL[2:0] Default 000 Description Waveform 2 Selection for Samples Mode. WAV2SEL[2:0] Source 000 Current 001 Voltage 010 Active power multiplier output 011 Reactive power multiplier output1 100 VA multiplier output 101 Irms LPF output Others Reserved Waveform 1 Selection for Samples Mode. WAV1SEL[2:0] Source 000 Current 001 Voltage 010 Active power multiplier output 011 Reactive power multiplier output1 100 VA multiplier output 101 Irms LPF output (low 24-bit) Others Reserved Waveform Samples Output Data Rate. DTRT[1:0] Update Rate (Clock = fCORE/5 = 819.2 kHz) 00 25.6 kSPS (clock/32) 01 12.8 kSPS (clock/64) 10 6.4 kSPS (clock/128) 11 3.2 kSPS (clock/256)
4 to 2
WAV1SEL[2:0]
000
1 to 0
DTRT[1:0]
00
1
This function is not available in the ADE5566 and ADE5166.
Table 35. No Load Configuration Register (NLMODE, 0x0E)
Bit 7 6 5 to 4 Mnemonic DISVARCMP1 IRMSNOLOAD VANOLOAD[1:0] Default 0 0 00 Description Setting this bit disables fundamental VAR gain compensation over line frequency. Logic 1 enables Irms no load threshold detection. The level is defined by the setting of the VANOLOAD bits. Apparent Power No Load Threshold. VANOLOAD[1:0] Result 00 No load detection disabled 01 No load detection enabled with threshold = 0.030% of full scale 10 No load detection enabled with threshold = 0.015% of full scale 11 No load detection enabled with threshold = 0.0075% of full scale
Rev. PrB | Page 38 of 148
Preliminary Technical Data
Bit 3 to 2 Mnemonic VARNOLOAD[1:0]1 Default 00
ADE5166/ADE5169/ADE5566/ADE5569
1 to 0
APNOLOAD[1:0]
00
Description Reactive Power No Load Threshold. VARNOLOAD[1:0] Result 00 No load detection disabled 01 No load detection enabled with threshold = 0.015% of full scale 10 No load detection enabled with threshold = 0.0075% of full scale 11 No load detection enabled with threshold = 0.0037% of full scale Active Power No Load Threshold. APNOLOAD[1:0] Result 00 No load detection disabled 01 No load detection enabled with threshold = 0.015% of full scale 10 No load detection enabled with threshold = 0.0075% of full scale 11 No load detection enabled with threshold = 0.0037% of full scale
1
This function is not available in the ADE5566 and ADE5166.
Table 36. Accumulation Mode Register (ACCMODE, 0x0F)
Bit 7 Mnemonic ICHANNEL1 Default 0 Description This bit indicates the current channel used to measure energy in antitampering mode. 0 = Channel A 1 = Channel B Configuration bit to select the event that triggers a fault interrupt. 0 = FAULTSIGN interrupt occurs when the part enters fault mode 1 = FAULTSIGN interrupt occurs when the part enters normal mode Configuration bit to select the event that triggers a reactive power sign interrupt. If set to 0, VARSIGN interrupt occurs when reactive power changes from positive to negative. If set to 1, VARSIGN interrupt occurs when reactive power changes from negative to positive. Configuration bit to select event that triggers an active power sign interrupt. If set to 0, APSIGN interrupt occurs when active power changes from positive to negative. If set to 1, APSIGN interrupt occurs when active power changes from negative to positive. Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output. Logic 1 enables reactive power accumulation depending on the sign of the active power. If active power is positive, VAR is accumulated as it is. If active power is negative, the sign of the VAR is reversed for the accumulation. This accumulation mode affects both the VAR registers (VARHR, RVARHR, LVARHR) and the pulse output when connected to VAR.2 Logic 1 enables positive-only accumulation of active power in energy register and pulse output. Logic 1 enables absolute value accumulation of active power in energy register and pulse output.
6
FAULTSIGN1
0
5
VARSIGN2
0
4
APSIGN
0
3 2
ABSVARM2 SAVARM2
0 0
1 0
1 2
POAM ABSAM
0 0
This function is not available in the ADE5566 and ADE5569. This function is not available in the ADE5566 and ADE5166.
Table 37. Gain Register (GAIN, 0x1B)
Bit 7 to 5 Mnemonic PGA2[2:0] Default 000 Description These bits define the voltage channel input gain. PGA2[2:0] Result 000 Gain = 1 001 Gain = 2 010 Gain = 4 011 Gain = 8 100 Gain = 16 Reserved. This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented. CFSIGN_OPT Result 0 Filtered power signal 1 On a per CF pulse basis
Rev. PrB | Page 39 of 148
4 3
Reserved CFSIGN_OPT
0 0
ADE5166/ADE5169/ADE5566/ADE5569
Bit 2 to 0 Mnemonic PGA1[2:0] Default 000 Description These bits define the current channel input gain. PGA1[2:0] Result 000 Gain = 11 001 Gain = 2 010 Gain = 4 011 Gain = 8 100 Gain = 16
Preliminary Technical Data
1
This gain is not recommended in the ADE5166 and ADE5169 because it can create an overranging of the ADC when both current inputs are in opposite phase.
Table 38. Mode 3 Register (MODE30x2B)
Bit No. 7 to 2 1 0 Mnemonic Reserved ZX1 ZX2 Default 0 0 0 Description Reserved Setting this bit enables the zero crossing output signal on P1.2 Setting this bit enables the zero crossing output signal on P0.5
Table 39. Calibration Mode Register (CALMODE, 0x3D)1
Bit 7 to 6 5 to 4 Mnemonic Reserved SEL_I_CH[1:0] Default 0 0 Description These bits should be kept cleared for proper operation. These bits define the current channel used for energy measurements. SEL_I_CH[1:0] Result 00 Current channel automatically selected by the tampering condition 01 Current channel connected to IPA 10 Current channel connected to IPB 11 Current channel automatically selected by the tampering condition Logic one short voltage channel to ground. Logic one short Current channels to ground. These bits should be kept clear for proper operation.
3 2 1 to 0
1
V_CH_SHORT I_CH_SHORT Reserved
0 0 0
This register is not available in the ADE5566 and ADE5569.
INTERRUPT STATUS/ENABLE SFRS
Table 40. Interrupt Status 1 SFR (MIRQSTL, 0xDC)
Bit 7 6 5 4 3 2 1 0
1 2
Interrupt Flag ADEIRQFLAG Reserved FAULTSIGN1 VARSIGN2 APSIGN VANOLOAD RNOLOAD2 APNOLOAD
Description This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt are set. This bit is automatically cleared when all of the enabled ADE status flags are cleared. Reserved. Logic 1 indicates that the fault mode has changed according to the configuration of the ACCMODE register. Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE register. Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register. Logic 1 indicates that an interrupt has been caused by apparent power no load detection. This interrupt is also used to reflect the part entering the Irms no load mode. Logic 1 indicates that an interrupt has been caused by reactive power no load detection. Logic 1 indicates that an interrupt has been caused by active power no load detection.
This function is not available in the ADE5566 and ADE5569. This function is not available in the ADE5566 and ADE5166.
Rev. PrB | Page 40 of 148
Preliminary Technical Data
Table 41. Interrupt Status 2 SFR (MIRQSTM, 0xDD)
Bit 7 6 5 4 3 2 1 0
1
ADE5166/ADE5169/ADE5566/ADE5569
Interrupt Flag CF2 CF1 VAEOF REOF1 AEOF VAEHF REHF1 AEHF
Description Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if CF2 pulse output is not enabled by clearing Bit 2 of the MODE1 register. Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if CF1 pulse output is not enabled by clearing Bit 1 of the MODE1 register. Logic 1 indicates that the VAHR register has overflowed. Logic 1 indicates that the VARHR register has overflowed. Logic 1 indicates that the WATTHR register has overflowed. Logic 1 indicates that the VAHR register is half full. Logic 1 indicates that the VARHR register is half full. Logic 1 indicates that the WATTHR register is half full.
This function is not available in the ADE5566 and ADE5166.
Table 42. Interrupt Status 3 SFR (MIRQSTH, 0xDE)
Bit 7 6 5 4 3 2 1 0 Interrupt Flag RESET Reserved WFSM PKI PKV CYCEND ZXTO ZX Description Indicates the end of a reset (for both software and hardware reset). Reserved. Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7). Logic 1 indicates that current channel has exceeded the IPKLVL value Logic 1 indicates that voltage channel has exceeded the VPKLVL value. Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles. Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles. Logic 1 indicates detection of a zero crossing in the voltage channel.
Table 43. Interrupt Enable 1 SFR (MIRQENL, 0xD9)
Bit 7 to 6 5 4 3 2 1 0
1 2
Interrupt Enable Bit Reserved FAULTSIGN1 VARSIGN2 APSIGN VANOLOAD RNOLOAD2 APNOLOAD
Description Reserved. When this bit is set, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core. When this bit is set, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the APSIGN flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
This function is not available in the ADE5566 and ADE5569. This function is not available in the ADE5566 and ADE5166.
Table 44. Interrupt Enable 2 SFR (MIRQENM, 0xDA)
Bit 7 6 5 4 3 2 1 0
1
Interrupt Enable Bit CF2 CF1 VAEOF REOF1 AEOF VAEHF REHF1 AEHF
Description When this bit is set, a CF2 pulse creates a pending ADE interrupt to the 8052 core. When this bit is set, a CF1 pulse creates a pending ADE interrupt to the 8052 core. When this bit is set, the VAEOF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the REOF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the AEOF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the VAEHF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the REHF flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
This function is not available in the ADE5566 and ADE5166.
Rev. PrB | Page 41 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Table 45. Interrupt Enable 3 SFR (MIRQENH, 0xDB)
Bit 7 to 6 5 4 3 2 1 0 Interrupt Enable Bit Reserved WFSM PKI PKV CYCEND ZXTO ZX
Preliminary Technical Data
Description Reserved. When this bit is set, the WFSM flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the PKI flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the PKV flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the CYCEND flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the ZXTO flag set creates a pending ADE interrupt to the 8052 core. When this bit is set, the ZX flag set creates a pending ADE interrupt to the 8052 core.
GAIN[7:0] 432 0 0 0
ANALOG INPUTS
Each ADE5166/ADE5169/ADE5566/ADE5569 has two fully differential voltage input channels. The maximum differential input voltage for input pairs VP/VN and IP/IN is 0.4 V for the ADE5566 and ADE5569. For the ADE5166 and ADE5169, PGA1 = 1 is not recommended because at full scale, when both IPA and IPB are 180 out of phase, the ADC can be overranged. It is recommended, for these products, that PGA1 = 2, 4, 8, or 16 be used. Each analog input channel has a programmable gain amplifier (PGA) with possible gain selections of 1, 2, 4, 8, and 16. The gain selections are made by writing to the GAIN register (see Table 37 and Figure 20). Bit 0 to Bit 2 select the gain for the PGA in the current channel, and Bit 5 to Bit 7 select the gain for the PGA in the voltage channel. For the ADE5166 and ADE5169, it is recommended that PGA1 = 2, 4, 8, or 16 be used. Figure 19 shows how a gain selection for the current channel is made using the gain register.
IP
7 0
6 0
5 0
1 0
0 0
GAIN (K) SELECTION
VIN
K x VIN
07411-018
IN
Figure 19. PGA in Current Channel
GAIN REGISTER* CURRENT AND VOLTAGE CHANNELS PGA CONTROL 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 ADDR: 0x1B
PGA2 GAIN SELECT 000 = x1 001 = x2 010 = x4 011 = x8 100 = x16
PGA1 GAIN SELECT 000 = x1 001 = x2 010 = x4 011 = x8 100 = x16
07411-019
CFSIGN_OPT RESERVED *REGISTER CONTENTS SHOW POWER-ON DEFAULTS.
Figure 20. Analog Gain Register
Rev. PrB | Page 42 of 148
Preliminary Technical Data
ANALOG-TO-DIGITAL CONVERSION
Each ADE5166/ADE5169/ADE5566/ADE5569 has two - analog-to-digital converters (ADCs). The outputs of these ADCs are mapped directly to waveform sampling SFRs (Address 0xE2 to Address 0xE7) and are used for energy measurement internal digital signal processing. In PSM1 (battery mode) and PSM2 (sleep mode), the ADCs are powered down to minimize power consumption. For simplicity, the block diagram in Figure 22 shows a firstorder - ADC. The converter is made up of the - modulator and the digital low-pass filter. A - modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE5166/ADE5169/ADE5566/ADE5569, the sampling clock is equal to 4.096 MHz/5. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and, therefore, the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples are averaged is a meaningful result obtained. This averaging is carried into the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit datawords that are proportional to the input signal level. The - converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE5166/ ADE5169/ADE5566/ADE5569 is 4.096 MHz/5 (819.2 kHz), and the band of interest is 40 Hz to 2 kHz. Oversampling has the
ADE5166/ADE5169/ADE5566/ADE5569
effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered (see Figure 21). However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of four is required to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. In the - modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. The result is that most of the noise is at the higher frequencies where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 21.
DIGITAL FILTER ANTIALIAS FILTER (RC) SHAPED NOISE SAMPLING FREQUENCY
SIGNAL
NOISE
0
2
409.6 FREQUENCY (kHz)
819.2
SIGNAL
HIGH RESOLUTION OUTPUT FROM DIGITAL LPF
NOISE
0
2
409.6 FREQUENCY (kHz)
819.2
Figure 21. Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator
MCLK/5 ANALOG LOW-PASS FILTER R C + - 24 VREF INTEGRATOR LATCHED COMPARATOR DIGITAL LOW-PASS FILTER
1-BIT DAC
Figure 22. First-Order - ADC
Rev. PrB | Page 43 of 148
07411-020
... 10100101 ...
07411-021
ADE5166/ADE5169/ADE5566/ADE5569
Antialiasing Filter
Figure 22 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing, an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC, which are higher than half the sampling rate of the ADC, appear in the sampled signal at a frequency below half the sampling rate. Figure 23 illustrates the effect. Frequency components (the black arrows) above half the sampling frequency (also known as the Nyquist frequency, that is, 409.6 kHz) are imaged or folded back down below 409.6 kHz. This happens with all ADCs regardless of the architecture. In Figure 23, only frequencies near the sampling frequency (819.2 kHz) move into the band of interest for metering (40 Hz to 2 kHz). This allows the use of a very simple LPF (low-pass filter) to attenuate high frequency (near 819.2 kHz) noise and prevents distortion in the band of interest. For conventional current sensors, a simple RC filter (single-pole LPF) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 819.2 kHz (see Figure 23). The 20 dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors. However, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This neutralizes the -20 dB per decade attenuation produced by one simple LPF. Therefore, when using a di/dt sensor, care should be taken to offset the 20 dB per decade gain. One simple approach is to cascade two RC filters to produce the -40 dB per decade attenuation needed.
Preliminary Technical Data
ALIASING EFFECTS
IMAGE FREQUENCIES
SAMPLING FREQUENCY
0
2
409.6 FREQUENCY (kHz)
819.2
Figure 23. ADC and Signal Processing in Current Channel Outline Dimensions
ADC Transfer Function
Both ADCs in the ADE5166/ADE5169/ADE5566/ADE5569 are designed to produce the same output code for the same input signal level. With a full-scale signal on the input of 0.4 V and an internal reference of 1.2 V, the ADC output code is nominally 2,147,483 or 0x20C49B. The maximum code from the ADC is 4,194,304; this is equivalent to an input signal level of 0.794 V. However, for specified performance, it is recommended that the full-scale input signal level of 0.4 V not be exceeded.
Current Channel ADC
Figure 24 shows the ADC and signal processing chain for the current channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (4.096 MHz/160). With the specified full-scale analog input signal of 0.4 V and PGA1 = 1, the ADC produces an output code that is approximately between 0x20C49B (+2,147,483d) and 0xDF3B65 (-2,147,483d). For inputs of 0.25 V, 0.125 V, 82.6 mV, and 31.3 mV with PGA1 = 2, 4, 8, and 16, respectively, the ADC produces an output code that is approximately between 0x28F5C2 (+2,684,354d) and 0xD70A3E (-2,684,354d).
MODE1[5] CURRENT RMS (I rms) CALCULATION WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION
x1, x2, x4 x8, x16 {GAIN[2:0]} IP I IN PGA1
REFERENCE DIGITAL INTEGRATOR* ADC HPF dt
50Hz V1 0.25V, 0.125V, 62.5mV, 31.3mV 0V 0x28F5C2 ANALOG INPUT RANGE 0x000000 0xD70A3E 0x2B7850 0x000000 0xD487B0 *WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A -20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT IS NOT FURTHER ATTENUATED. PGA1 = 1 IS NOT RECOMMENDED IN THE ADE5166 AND ADE5169. CURRENT CHANNEL WAVEFORM DATA RANGE 60Hz 0xCBD330 CURRENT CHANNEL WAVEFORM DATA RANGE AFTER INTEGRATOR (60Hz) 0x342CD0 0x000000
CURRENT CHANNEL WAVEFORM DATA RANGE AFTER INTEGRATOR (50Hz)
Figure 24. ADC and Signal Processing in Current Channel with PGA1 = 1, 2, 4, 8, or 16 for ADE5566 and ADE5569
Rev. PrB | Page 44 of 148
07411-023
07411-022
Preliminary Technical Data
IPA I IN PGA1 IBP x1, x2, x4, x8, x16 {GAIN[2:0]} PGA1 INTEGRATOR ADC HPF dt ADC MULTIPLIER LPF2
ADE5166/ADE5169/ADE5566/ADE5569
WGAIN[11:0]
HPF IBGAIN[11:0] 2
CF1NUM[15:0] WATTOS[15:0] VARGAIN[11:0] DFC LPF2 CF1DEN[15:0] IRMSOS[11:0] VAROS[15:0] VAGAIN[11:0] CF2NUM[15:0] CF1
x2
LPF VRMSOS[11:0] VARDIV[7:0]
DFC
CF2
VP VN PGA2 ADC HPF
CF2DEN[15:0]
x2
LPF
VADIV[7:0]
%
%
%
WDIV[7:0]
METERING SFRs
Figure 25. ADC and Signal Processing in Current Channel with PGA1 = 2, 4, 8, or 16 for ADE5166 and ADE5169
VP V2 VN 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV V2
x1, x2, x4, x8, x16 {GAIN[7:5]}
REFERENCE
ACTIVE AND REACTIVE POWER CALCULATION
HPF PGA2 ADC
VOLTAGE RMS (Vrms) CALCULATION
WAVEFORM SAMPLE REGISTER VOLTAGE PEAK DETECT ZX DETECTION
0V
VOLTAGE CHANNEL WAVEFORM DATA RANGE ANALOG INPUT RANGE 0x28F5 0x0000
f-3dB = 63.7Hz
LPF1
ZX SIGNAL DATA RANGE FOR 60Hz SIGNAL 0x1DD0 0x0000 0xE230
MODE1[6]
0xD70B
ZX SIGNAL DATA RANGE FOR 50Hz SIGNAL 0x2037 0x0000 0xDFC9
07411-024
Figure 26. ADC and Signal Processing in Voltage Channel
Rev. PrB | Page 45 of 148
07411-092
ADE5166/ADE5169/ADE5566/ADE5569
Voltage Channel ADC
Figure 26 shows the ADC and signal processing chain for the voltage channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces an output code that is approximately between 0x28F5 (+10,485d) and 0xD70B (-10,485d).
Preliminary Technical Data
Channel Selection Indication
The current channel selected for measurement is indicated by Bit 7 (ICHANNEL) in the ACCMODE register (0x0F). When this bit is cleared, IPA is selected and, when it is set, IPB is selected. The ADE5166/ADE5169 automatically switch from one channel to the other and report the channel configuration in the ACCMODE register (0x0F).. The current channel selected for measurement can also be forced. Setting the SEL_I_CH[1:0] bits in the CALMODE register (0x3D) selects IPA and IPB, respectively. When both bits are cleared or set, the current channel used for measurement is selected automatically based on the fault detection.
Channel Sampling
The waveform samples of the current ADC and voltage ADC can also be routed to the waveform registers to be read by the MCU core. The active, reactive, apparent power, and energy calculation remain uninterrupted during waveform sampling. When in waveform sampling mode, one of four output sample rates can be chosen by using the DTRT[1:0] bits of the WAVMODE register (see Table 34). The output sample rate can be 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. If the WFSM enable bit is set in the Interrupt Enable 3 SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE interrupt. The sampled signals selected in the WAVMODE register are latched into the waveform SFRs when the waveform high byte (WAV1H or WAV2H) is read. The ADE interrupt stays active until the WFSM status bit is cleared (see the Energy Measurement Interrupts section).
Fault Indication
The ADE5166/ADE5169 provide an indication of the part going in or out of a fault condition. The new fault condition is indicated by the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, 0xDC). When FAULTSIGN bit (Bit 6) of the ACCMODE register (0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set when the part is a entering fault condition or a normal condition. When the FAULTSIGN bit is set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), and the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set, the 8052 core has a pending ADE interrupt.
FAULT DETECTION1
The ADE5166/ADE5169 incorporate a fault detection scheme that warns of fault conditions and allows the ADE5166/ADE5169 to continue accurate measurement during a fault event. The ADE5166/ADE5169 do this by continuously monitoring both current inputs (IPA and IPB). For ease of understanding, these currents are referred to as phase and neutral (return) currents. In the ADE5166/ADE5169, a fault condition is defined when the difference between IPA and IPB is greater than 6.25% of the active channel. If a fault condition is detected and the inactive channel is larger than the active channel, the ADE5166/ADE5169 automatically switch current measurement to the inactive channel. During a fault, the active, reactive, current rms and apparent powers are generated using the larger of the two currents. On power-up, IPA is the current input selected for active, reactive, and apparent power and Irms calculations. To prevent a false alarm, averaging is done for the fault detection, and a fault condition is detected approximately one second after the event. The fault detection is automatically disabled when the voltage signal is less than 0.3% of the fullscale input range. This eliminates false detection of a fault due to noise at light loads. Because the ADE5166/ADE5169 look for a difference between the voltage signals on IPA and IPB, it is important that both current transducers be closely matched.
Fault with Active Input Greater Than Inactive Input
If IPA is the active current input (that is, being used for billing), and the voltage signal on IPB (inactive input) falls below 93.75% of IPA, and the FAULTSIGN bit (Bit 6) of the ACCMODE register (0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set. Both analog inputs are filtered and averaged to prevent false triggering of this logic output. As a consequence of the filtering, there is a time delay of approximately three seconds on the logic output after the fault event. The FAULTSIGN flag is independent of any activity. Because IPA is the active input and it is still greater than IPB, billing is maintained on IPA; that is, no swap to the IPB input occurs. IPA remains the active input.
Fault with Inactive Input GreaterThan Active Input
If the difference between IPB, the inactive input, and IPA, the active input (that is, being used for billing), becomes greater than 6.25% of IPB, and the FAULTSIGN bit (Bit 6) of the ACCMODE register (0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set. The analog input IPB becomes the active input. Again, a time constant of about 3 sec is associated with this swap. IPA does not swap back to the active channel until IPA is greater than IPB and the difference between IPA and IPB, in this order, becomes greater than 6.25% of IPB. However, if the FAULTSIGN bit (Bit 6) of the ACCMODE register (0x0F) is set, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set as soon as IPA is within 6.25% of IPB. This threshold eliminates potential chatter between IPA and IPB.
1
This function is not available in the ADE5566 and ADE5569.
Rev. PrB | Page 46 of 148
Preliminary Technical Data
Calibration Concerns
Typically, when a meter is being calibrated, the voltage and current circuits are separated, as shown in Figure 27. This means that current passes through only the phase or neutral circuit. Figure 27 shows current being passed through the phase circuit. This is the preferred option because the ADE5166/ ADE5169 start billing on the input IPA on power-up. The phase circuit CT is connected to IPA in the diagram. Because the current sensors are not perfectly matched, it is important to match current inputs. The ADE5166/ADE5169 provide a gain calibration register for IPB, IBGAIN (Address 0x1C). IBGAIN is a 12-bit, signed, twos complement register that provides a gain resolution of 0.0244%/LSB. For calibration, a first measurement should be done on IPA by setting the SEL_I_CH bits to 0b01 in the CALMODE register (0x3D). This measurement should be compared to the measurement on IPB. Measuring IPB can be forced by setting the SEL_I_CH bits to 0b10 in the CALMODE register (0x3D). The gain error between these two measurements can be evaluated using
Error (% ) = Measurement (I B ) - Measurement (I A ) Measurement (I A )
ADE5166/ADE5169/ADE5566/ADE5569
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR FOR THE ADE5569/ADE5169
A di/dt sensor, a feature available for the AD5569/ADE5169 but not for the AD5566/ADE5166, detects changes in the magnetic field caused by ac currents. Figure 28 shows the principle of a di/dt current sensor.
MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT)
Figure 28. Principle of a di/dt Current Sensor
The two channels IPA and IPB can then be matched by writing -Error(%)/(1 + Error(%)) x 212 to the IBGAIN register. This matching adjustment is valid for all energy measurements made by the ADE5166/ADE5169., including active power, reactive power, Irms, and apparent power,
IPB 0 CT RB AGND IN TEST CURRENT NEUTRAL RB CT RA CF RF 0V CF RF IPA
The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE5569/ADE5169 have a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on the current channel is switched off by default when the ADE5569/ADE5169 are powered up. Setting the INTE bit in the MODE1 register (0x0B) turns on the integrator. Figure 29 to Figure 32 show the gain and phase response of the digital integrator.
10
VA
CF
PHASE
RF RF CT
VP VN
IB
0
-10
240V rms
GAIN (dB)
V
07411-025
-20
Figure 27. Fault Conditions for Inactive Input Greater Than Active Input
-30
-40
100 FREQUENCY (Hz)
1000
Figure 29. Combined Gain Response of the Digital Integrator and Phase Compensator
Rev. PrB | Page 47 of 148
07411-027
-50
07411-026
+ EMF (ELECTROMOTIVE FORCE) - INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY (di/dt)
ADE5166/ADE5169/ADE5566/ADE5569
-88.0
Preliminary Technical Data
-89.70 -89.75
-88.5
-89.80
PHASE (Degrees)
PHASE (Degrees)
-89.0
-89.85 -89.90 -89.95 -90.00
-89.5
-90.0
-90.05
-90.5 102 FREQ FREQUENCY (Hz) 103
40
45
50
55 60 FREQUENCY (Hz)
65
70
Figure 30. Combined Phase Response of the Digital Integrator and Phase Compensator
-1.0 -1.5 -2.0 -2.5
GAIN (dB)
Figure 32. Combined Phase Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
-3.0 -3.5 -4.0 -4.5 -5.0 -5.5 45 50 55 60 FREQUENCY (Hz) 65 70
07411-029
Note that the integrator has a -20 dB/dec attenuation and an approximately -90 phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. The di/dt sensor has a 20 dB/dec gain associated with it. It also generates significant high frequency noise. Therefore, a more effective antialiasing filter is needed to avoid noise due to aliasing (see the Antialiasing Filter section). When the digital integrator is switched off, the ADE5569/ADE5169 can be used directly with a conventional current sensor, such as a current transformer (CT), or with a low resistance current shunt.
-6.0 40
Figure 31. Combined Gain Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
Rev. PrB | Page 48 of 148
07411-030
07411-106
Preliminary Technical Data
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
Each ADE5166/ADE5169/ADE5566/ADE5569 has a zerocrossing detection circuit on the voltage channel. This external zero-crossing signal can be output on P0.5 and P1.2 (see Table 38. It is also used in calibration mode. The zero crossing is generated by default from the output of LPF1. This filter has a low cutoff frequency and is intended for 50 Hz and 60 Hz systems. If needed, this filter can be disabled to allow a higher frequency signal to be detected or to limit the group delay of the detection. If the voltage input fundamental frequency is below 60 Hz, and a time delay in ZX detection is acceptable, it is recommended to enable LPF1. Enabling LPF1 limits the variability in the ZX detection by eliminating the high frequency components. Figure 33 shows how the zero-crossing signal is generated.
x1, x2, x4, x8, x16 VP V2 VN ZERO CROSS LPF1 f-3dB = 63.7Hz
ZX
ADE5166/ADE5169/ADE5566/ADE5569
before a zero crossing is detected in the Interrupt Status 3 SFR (MIRQSTH, 0xDE), and the ZXTO bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the ZXTO status bit is cleared (see the Energy Measurement Interrupts section). The ZXTOUT register (Address 0x11) can be written to or read by the user (see the Energy Measurement Register List section). The resolution of the register is 160/MCLK seconds per LSB. Thus, the maximum delay for an interrupt is 0.16 seconds (1/MCLK x 212) when MCLK = 4.096 MHz. Figure 34 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than MCLK/160 x ZXTOUT seconds.
12-BIT INTERNAL REGISTER VALUE ZXTOUT
REFERENCE
HPF
{GAIN[7:5]} PGA2 ADC 2
VOLTAGE CHANNEL
MODE1[6] 1.0 0.73 43.24 @ 60Hz ZX
Figure 34. Zero-Crossing Timeout Detection
Period or Frequency Measurements
The ADE5166/ADE5169/ADE5566/ADE5569 provide the period or frequency measurement of the line. The period or frequency measurement is selected by clearing or setting the FREQSEL bit in the MODE2 register (0x0C). The period/ frequency register, PER_FREQ Register (0x0A), is an unsigned 16-bit register that is updated every period. If LPF1 is enabled, a settling time of 1.8 seconds is associated with this filter before the measurement is stable. When the period measurement is selected, the measurement has a 2.44 s/LSB (4.096 MHz/10), which represents 0.014% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the period register is approximately 0d6827. The length of the register enables the measurement of line frequencies as low as 12.5 Hz. The period register is stable at 1 LSB when the line is established and the measurement does not change. When the frequency measurement is selected, the measurement has a 0.0625 Hz/LSB resolution when MCLK = 4.096 MHz, which represents 0.104% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the frequency register is 0d960. The frequency register is stable at 4 LSB when the line is established and the measurement does not change.
V2
LPF1
Figure 33. Zero-Crossing Detection on the Voltage Channel
The zero-crossing signal ZX is generated from the output of LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at MCLK = 4.096 MHz). As a result, there is a phase lag between the analog input signal V2 and the output of LPF1. The phase lag response of LPF1 results in a time delay of approximately 2 ms (@ 60 Hz) between the zero crossing on the analog inputs of the voltage channel and ZX detection. The zero-crossing detection also drives the ZX flag in the Interrupt Status 3 SFR (MIRQSTH, 0xDE). If the ZX bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the ZX status bit is cleared (see the Energy Measurement Interrupts section).
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 160/MCLK seconds. The register is reset to its user programmed, full-scale value every time a zero crossing is detected on the voltage channel. The default power-on value in this register is 0xFFF. If the internal register decrements to 0
07411-031
Line Voltage SAG Detection
In addition to detection of the loss of the line voltage signal (zero crossing), the ADE5166/ADE5169/ADE5566/ADE5569
Rev. PrB | Page 49 of 148
07411-032
ZXTO FLAG BIT
ADE5166/ADE5169/ADE5566/ADE5569
can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. This condition is illustrated in Figure 35.
VOLTAGE CHANNEL FULL SCALE SAGLVL[15:0]
Preliminary Technical Data
V2
VPKLVL[15:0]
PKV RESET LOW WHEN MIRQSTH SFR IS READ
SAG RESET LOW WHEN VOLTAGE CHANNEL EXCEEDS SAGLVL[15:0] AND SAG FLAG RESET
07411-033
PKV INTERRUPT FLAG RESET BIT PKV IN MIRQSTH SFR
07411-034
SAG FLAG
SAGCYC[7:0] = 0x04 3 LINE CYCLES
Figure 36. Peak Level Detection
Figure 35. SAG Detection
Figure 35 shows the line voltage falling below a threshold that is set in the SAG level register (SAGLVL[15:0]) for three line cycles. The quantities 0 and 1 are not valid for the SAGCYC register, and the contents represent one more than the desired number of full line cycles. For example, when the SAG cycle (SAGCYC[7:0]) contains 0x04, FSAG in the power management interrupt flag SFR (IPSMF, 0xF8) is set at the end of the third line cycle after the line voltage falls below the threshold. If the SAG enable bit (ESAG) in the power management interrupt enable SFR (IPSME, 0xEC) is set, the 8052 core has a pending power supply management interrupt. The PSM interrupt stays active until the ESAG bit is cleared (see the Power Supply Management Interrupt (PSM) section). In Figure 35, the SAG flag (FSAG) is set on the fifth line cycle after the signal on the voltage channel first dropped below the threshold level.
Figure 36 shows a line voltage exceeding a threshold that is set in the voltage peak register (VPKLVL[15:0]). The voltage peak event is recorded by setting the PKV flag in the Interrupt Status 3 SFR (MIRQSTH, 0xDE). If the PKV enable bit is set in the Interrupt Enable 3 SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE interrupt. Similarly, the current peak event is recorded by setting the PKI flag in Interrupt Status 3 SFR (MIRQSTH, 0xDE). The ADE interrupt stays active until the PKV or PKI status bit is cleared (see the Energy Measurement Interrupts section).
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are compared to the absolute value of the voltage and 2 MSBs of the current channel, respectively. Thus, for example, the nominal maximum code from the current channel ADC with a full-scale signal is 0x28F5C2 (see the Current Channel ADC section). Therefore, writing 0x28F5 to the IPKLVL register puts the current channel, peak detection level at full scale and sets the current peak detection to its least sensitive value. Writing 0x00 puts the current channel detection level at 0. The detection is done by comparing the contents of the IPKLVL register to the incoming current channel sample. The PKI flag indicates that the peak level is exceeded. If the PKI or PKV bit is set in the Interrupt Enable 3 SFR (MIRQENH, 0xDB), the 8052 core has a pending ADE interrupt.
SAG Level Set
The 2-byte contents of the SAG level register (SAGLVL, 0x14) are compared to the absolute value of the output from LPF1. Therefore, when LPF1 is enabled, writing 0x2038 to the SAG level register puts the SAG detection level at full scale (see Figure 35). Writing 0x00 or 0x01 puts the SAG detection level at 0. The SAG level register is compared to the input of the ZX detection, and detection is made when the contents of the SAG level register are greater.
Peak Level Record
Each ADE5166/ADE5169/ADE5566/ADE5569 records the maximum absolute value reached by the voltage and current channels in two different registers, IPEAK and VPEAK, respectively. Each register is a 24-bit unsigned register that is updated each time the absolute value of the waveform sample from the corresponding channel is above the value stored in the VPEAK or IPEAK register. The contents of the VPEAK register correspond to the maximum absolute value observed on the voltage channel input. The contents of IPEAK and VPEAK represent the maximum absolute value observed on the current and voltage input, respectively. Reading the RSTVPEAK and RSTIPEAK registers clears their respective contents after the read operation.
Peak Detection
The ADE5166/ADE5169/ADE5566/ADE5569 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 36 illustrates the behavior of the peak detection for the voltage channel. Both voltage and current channels are monitored at the same time.
Rev. PrB | Page 50 of 148
Preliminary Technical Data
PHASE COMPENSATION
The ADE5166/ADE5169/ADE5566/ADE5569 must work with transducers that can have inherent phase errors. For example, a phase error of 0.1 to 0.3 is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE5166/ADE5169/ ADE5566/ADE5569 provide a means of digitally calibrating these small phase errors. The part allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. Because the compensation is in time, this technique should only be used for small phase errors in the range of 0.1 to 0.5. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. The phase calibration register (PHCAL[7:0]) is a twos complement, signed, single-byte register that has values ranging from 0x82 (-126d) to 0x68 (+104d). The PHCAL register is centered at 0x40, meaning that writing 0x40 to the register gives 0 delay. By changing this register, the time delay in the voltage channel signal path can change from -231.93 s to +48.83 s (MCLK = 4.096 MHz). One LSB is equivalent to a 1.22 s (4.096 MHz/5) time delay or advance. A line frequency of 60 Hz gives a phase resolution of 0.026 at the fundamental (that is, 360 x 1.22 s x 60 Hz). Figure 37 illustrates how the phase compensation is used to remove a 0.1 phase lead in the current channel due to the external transducer. To cancel the lead (0.1) in the current channel, a phase lead must also be introduced into the voltage channel. The resolution of the phase adjustment allows the introduction of a phase lead in increments of 0.026. The phase lead is achieved by introducing a time advance into the voltage channel. A time advance of 4.88 s is made by writing -4 (0x3C) to the time delay block, thus reducing the amount of time delay by 4.88 s, or equivalently, a phase lead of approximately 0.1 at a line frequency of 60 Hz (0x3C represents -4 because the register is centered with 0 at 0x40).
IP/IPA I IN PGA1 ADC 1
ADE5166/ADE5169/ADE5566/ADE5569
RMS CALCULATION
The root mean square (rms) value of a continuous signal V(t) is defined as
Vrms =
1 x V 2 (t ) dt T
0
T
(1)
For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. The ADE5166/ADE5169/ADE5566/ADE5569 implement this method by serially squaring the input, averaging them, and then taking the square root of the average. The averaging part of this signal processing is done by implementing a low-pass filter (LPF3 in Figure 38, Figure 40, and Figure 41). This LPF has a -3 dB cutoff frequency of 2 Hz when MCLK = 4.096 MHz.
V (t ) = 2 x V sin(t ) where V is the rms voltage.
(2)
V 2 (t ) = V 2 - V 2 cos(2t )
(3)
When this signal goes through LPF3, the cos(2t) term is attenuated and only the dc term Vrms2 (shown as V2 in Figure 38) goes through.
V 2 (t ) = V 2 - V 2 cos(2t) V (t ) = 2 x V sin(t ) LPF3 INPUT V
07411-036
V 2 (t) = V 2
Figure 38. RMS Signal Processing
The Irms signal can be read from the waveform register by setting the WAVMODE register (0x0D) and setting the WFSM bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB). Like the current and voltage channels waveform sampling modes, the waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. It is important to note that when the current input is larger than 40% of full scale, the Irms waveform sample register does not represent the true processed rms value. The rms value processed with this level of input is larger than the 24-bit read by the waveform register, making the value read truncated on the high end.
HPF
24 LPF2
24
VP V VN V 0.1 I PGA2 ADC 2
1
DELAY BLOCK 1.22s/LSB 7 0
CHANNEL 2 DELAY REDUCED BY 4.48s (0.1LEAD AT 60Hz) 0x0B IN PHCAL[7:0] V I
1 0010111 PHCAL[7:0] -231.93s TO +48.83s
60Hz
Figure 37. Phase Calibration
Rev. PrB | Page 51 of 148
07411-035
60Hz
ADE5166/ADE5169/ADE5566/ADE5569
Current Channel RMS Calculation
Each ADE5166/ADE5169/ADE5566/ADE5569 simultaneously calculates the rms values for the current and voltage channels in different registers. Figure 39 and Figure 40 show the detail of the signal processing chain for the rms calculation on the current channel. The current channel rms value is processed from the samples used in the current channel waveform sampling mode and is stored in an unsigned 24-bit register (Irms). One LSB of the current channel rms register is equivalent to one LSB of a current channel waveform sample. The update rate of the current channel rms measurement is 4.096 MHz/5. To minimize noise in the reading of the register, the Irms register can also be configured to update only with the zero crossing of the voltage input. This configuration is done by setting the ZXRMS bit in the MODE2 register (0x0C). With the different specified full-scale analog input signal PGA1 values, the ADC produces an output code that is approximately 0d2,147,483 (PGA1 = 1) or 0d2,684,354 (PGA1 = 2, 4, 8, or 16); see the Current Channel ADC section. Similarly, the equivalent rms value of a full-scale ac signal is 0d1,518,499 (0x172BA3) when PGA = 1 and 0d1,898,124 (0x1CF68C) when PGA1 = 2,
60Hz
Preliminary Technical Data
4, 8, or 16. The current rms measurement provided in the ADE5166/ADE5169/ADE5566/ADE5569 is accurate to within 0.5% for signal inputs between full scale and full scale/500. The conversion from the register value to amps must be done externally in the microprocessor using an amps/LSB constant.
Current Channel RMS Offset Compensation
The ADE5166/ADE5169/ADE5566/ADE5569 incorporate a current channel rms offset compensation register (IRMSOS). This is a 12-bit signed register that can be used to remove offset in the current channel rms calculation. An offset can exist in the rms calculation due to input noises that are integrated into the dc component of V2(t). One LSB of the current channel rms offset is equivalent to 16,384 LSBs of the square of the current channel rms register. Assuming that the maximum value from the current channel rms calculation is 0d1,898,124 with full-scale ac inputs, then 1 LSB of the current channel rms offset represents 0.23% of measurement error at -60 dB down from full scale.
I rms = I rms 0 2 + IRMSOS x 32768
(4)
where Irms0 is the rms measurement without offset correction.
CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR ON (60Hz)
0x2B7850 0x000000 0xD487B0
MODE1[5] IP HPF sgn 225 DIGITAL INTEGRATOR* dt HPF1 LPF3
IRMSOS[11:0] 226 227 218 217 216
Irms(t)
0x00
24
+
24
Irms[23:0]
IPB
HPF
CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR OFF 0x28F5C2 0x000000 0xD70A3E
07411-037
NOTES: 1. WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A -20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT IS NOT FURTHER ATTENUATED.
Figure 39. ADE5566/ADE5569 Current Channel RMS Signal Processing with PGA1 = 1, 2, 4, 8, or 16
Rev. PrB | Page 52 of 148
Preliminary Technical Data
60Hz
0x2B7850 0x000000 0xD487B0
ADE5166/ADE5169/ADE5566/ADE5569
CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR ON (60Hz)
MODE1[5] IPA HPF DIGITAL INTEGRATOR* dt
IRMSOS[11:0] sgn 225 226 227 HPF1 LPF3 218 217 216
Irms(t)
0x00
24
+
24
Irms[23:0]
IPB
HPF
IBGAIN
CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR OFF 0x28F5C2 0x000000 0xD70A3E
07411-116
NOTES: 1. WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A -20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT IS NOT FURTHER ATTENUATED.
Figure 40. ADE5166/ADE5169 Current Channel RMS Signal Processing with PGA1 = 2, 4, 8, or 16
VOLTAGE SIGNAL (V(t)) 0x28F5 0x0 0xD70B LPF1 VOLTAGE CHANNEL LPF3 + VRMOS[11:0] sgn 216 215 28 27 26 + VRMSx[23:0] 0x28F5C2
07411-038
0x00
Figure 41. Voltage Channel RMS Signal Processing
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ADE5166/ADE5169/ADE5566/ADE5569
Voltage Channel RMS Calculation
Figure 41 shows details of the signal processing chain for the rms calculation on the voltage channel. The voltage channel rms value is processed from the samples used in the voltage channel waveform sampling mode and is stored in the unsigned 24-bit Vrms register. The update rate of the voltage channel rms measurement is MCLK/5. To minimize noise in the reading of the register, the Vrms register can also be configured to update only with the zero crossing of the voltage input. This configuration is done by setting the ZXRMS bit in the MODE2 register (0x0C). With the specified full-scale ac analog input signal of 0.4 V, the output from the LPF1 in Figure 41 swings between 0x28F5 and 0xD70B at 60 Hz (see the Voltage Channel ADC section). The equivalent rms value of this full-scale ac signal is approximately 0d1,898,124 (0x1CF68C) in the Vrms register. The voltage rms measurement provided in the ADE5166/ADE5169/ADE5566/ ADE5569 is accurate to within 0.5% for signal input between full scale and full scale/20. The conversion from the register value to volts must be done externally in the microprocessor using a V/LSB constant.
Preliminary Technical Data
The average power over an integral number of line cycles (n) is given by the expression in Equation 9.
P= 1 nT
0
nT
p(t )dt = VI
(9)
where: T is the line cycle period. P is referred to as the active or real power. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 9, that is, VI. This is the relationship used to calculate active power in the ADE5166/ ADE5169/ADE5566/ADE5569. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information. This process is illustrated in Figure 42.
INSTANTANEOUS POWER SIGNAL 0x19999A ACTIVE REAL POWER SIGNAL = v x i p(t) = v x i - v x i x cos(2t)
VI 0xCCCCD
Voltage Channel RMS Offset Compensation
The ADE5166/ADE5169/ADE5566/ADE5569 incorporate a voltage channel rms offset compensation register (VRMSOS). This is a 12-bit signed register that can be used to remove offset in the voltage channel rms calculation. An offset can exist in the rms calculation due to input noises and dc offset in the input samples. One LSB of the voltage channel rms offset is equivalent to 64 LSBs of the rms register. Assuming that the maximum value from the voltage channel rms calculation is 0d1,898,124 with full-scale ac inputs, then 1 LSB of the voltage channel rms offset represents 3.37% of measurement error at -60 dB down of full scale. Vrms = Vrms0 + 64 x VRMSOS where Vrms0 is the rms measurement without offset correction. (5)
0x00000 CURRENT i(t) = 2 x i x sin(t) VOLTAGE v(t) = 2 x v x sin(t)
07411-039
Figure 42. Active Power Calculation
ACTIVE POWER CALCULATION
Active power is defined as the rate of energy flow from source to load. It is the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at every instant of time. The unit of power is the watt or joules/second. Equation 8 gives an expression for the instantaneous power signal in an ac system.
v (t ) = 2 x V sin(t ) i (t ) = 2 x I sin(t )
Because LPF2 does not have an ideal brick wall frequency response (see Figure 43), the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because of its sinusoidal nature, the ripple is removed when the active power signal is integrated to calculate energy (see the Active Energy Calculation section).
0
-4
ATTENUATION (dB)
-8
-12
(6) (7)
-16
1
3
p (t ) = v (t ) x i (t )
p(t ) = VI - VI cos(2t )
10 FREQUENCY (Hz)
30
100
Figure 43. Frequency Response of LPF2
(8)
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07411-040
where: v is the rms voltage. i is the rms current.
-20
-24
Preliminary Technical Data
Active Power Gain Calibration
Figure 44 shows the signal processing chain for the active power calculation in the ADE5166/ADE5169/ADE5566/ADE5569. As explained previously, the active power is calculated by filtering the output of the multiplier with a low-pass filter. Note that when reading the waveform samples from the output of LPF2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (WGAIN[11:0]). The gain is adjusted by writing a twos complement 12-bit word to the watt gain register. Equation 10 shows how the gain adjustment is related to the contents of the watt gain register.
ADE5166/ADE5169/ADE5566/ADE5569
Active Power Sign Detection
The ADE5166/ADE5169/ADE5566/ADE5569 detect a change of sign in the active power. The APSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) records when a change of sign has occurred according to Bit APSIGN in the ACCMODE register (0x0F). If the APSIGN flag is set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APSIGN status bit is cleared (see the Energy Measurement Interrupts section). When APSIGN in the ACCMODE register (0x0F) is cleared (default), the APSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set when a transition from positive-tonegative active power has occurred. When APSIGN in the ACCMODE register (0x0F) is set, the APSIGN flag in the MIRQSTL SFR is set when a transition from negative to positive active power occurs.
WGAIN Output WGAIN = Active Power x 1 + 212
(10)
For example, when 0x7FF is written to the watt gain register, the power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5). Similarly, 0x800 = -2048d (signed, twos complement) and power output is scaled by -50%. Each LSB scales the power output by 0.0244%. The minimum output range is given when the watt gain register contents are equal to 0x800 and the maximum range is given by writing 0x7FF to the watt gain register. This can be used to calibrate the active power (or energy) calculation in the ADE5166/ADE5169/ADE5566/ADE5569.
Active Power No Load Detection
The ADE5166/ADE5169/ADE5566/ADE5569 include a no load threshold feature on the active energy that eliminates any creep effects in the meter. The part accomplishes this by not accumulating energy if the multiplier output is below the no load threshold. When the active power is below the no load threshold, the APNOLOAD flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set. If the APNOLOAD bit is set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APNOLOAD status bit is cleared (see the Energy Measurement Interrupts section). The no load threshold level is selectable by setting the APNOLOAD bits in the NLMODE register (0x0E). Setting these bits to 0b00 disables the no load detection, and setting them to 0b01, 0b10, or 0b11 sets the no load detection threshold to 0.015%, 0.0075%, or 0.0037% of the multiplier full-scale output frequency, respectively. The IEC 62053-21 specification states that the meter must start up with a load equal to or less than 0.4% IPB, which translates to 0.0167% of the full-scale output frequency of the multiplier.
Active Power Offset Calibration
The ADE5166/ADE5169/ADE5566/ADE5569 also incorporate an active power offset register (WATTOS[15:0]). It is a signed, twos complement, 16-bit register that can be used to remove offsets in the active power calculation (see Figure 42). An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed. The 256 LSBs (WATTOS = 0x0100) written to the active power offset register are equivalent to 1 LSB in the waveform sample register. Assuming the average value, output from LPF2 is 0xCCCCD (838,861d) when inputs on the voltage and current channels are both at full scale. At -60 dB down on the current channel (1/1000 of the current channel full-scale input), the average word value output from LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output has a measurement error of 1/838.861 x 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register. Therefore, the power offset correction resolution is 0.000464%/LSB (0.119%/256) at -60 dB.
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ADE5166/ADE5169/ADE5566/ADE5569
ACTIVE ENERGY CALCULATION
As stated in the Active Power Calculation section, power is defined as the rate of energy flow. This relationship can be expressed mathematically in Equation 11.
Preliminary Technical Data
accumulation. The active power signal in the waveform register is continuously added to the internal active energy register. The active energy accumulation depends on the setting of the POAM and ABSAM bits in the ACCMODE register (0x0F). When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the active energy contents. When both bits are set, the ADE5166/ADE5169/ADE5566/ ADE5569 are set to be in the more restrictive mode, the positiveonly accumulation mode. When POAM in the ACCMODE register (0x0F) is set, only positive power contributes to the active energy accumulation. When ABSAM in the ACCMODE register (0x0F) is set, the absolute active power is used for the active energy accumulation (see the Watt-Absolute Accumulation Mode section). The output of the multiplier is divided by the value in the WDIV register. If the value in the WDIV register is equal to 0, the internal active energy register is divided by 1. WDIV is an 8-bit unsigned register. After dividing by WDIV, the active energy is accumulated in a 49-bit internal energy accumulation register. The upper 24 bits of this register are accessible through a read to the active energy register (WATTHR[23:0]). A read to the RWATTHR register returns the content of the WATTHR register, and the upper 24 bits of the internal register are cleared. As shown in Figure 44, the active power signal is accumulated in an internal 49-bit signed register. The active power signal can be read from the waveform register by setting the WAVMODE register (0x0D) and setting the WFSM bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB). Like the current and voltage channels waveform sampling modes, the waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS.
P=
dE dt
(11)
where: P is power. E is energy. Conversely, energy is given as the integral of power.
E = P (t )dt
(12)
The ADE5166/ADE5169/ADE5566/ADE5569 achieve the integration of the active power signal by continuously accumulating the active power signal in an internal, nonreadable, 49-bit energy register. The register (WATTHR[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 13 expresses the relationship.
E = p (t ) dt = lim p ( nT ) x T t 0 n =1
where: n is the discrete time sample number. T is the sample period.
(13)
The discrete time sample period (T) for the accumulation register in the ADE5166/ADE5169/ADE5566/ADE5569 is 1.22 s (5/MCLK). In addition to calculating the energy, this integration removes any sinusoidal components that may be in the active power signal. Figure 44 shows this discrete time integration or
FOR WAVEFORM SAMPLING
23
WATTHR[23:0]
UPPER 24 BITS ARE ACCESSIBLE THROUGH WATTHR[23:0] REGISTER 0
WATTOS[15:0] sgn 26 25 CURRENT CHANNEL
LPF2 2-6 2-7 2-8 WDIV[7:0] + + VOLTAGE CHANNEL ACTIVE POWER SIGNAL WGAIN[11:0] OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL ACTIVE ENERGY REGISTER 48 0
+
+
%
TO DIGITAL-TO-FREQUENCY CONVERTER WAVEFORM REGISTER VALUES
T
OUTPUT LPF2
5 MCLK
TIME (nT)
Figure 44. Active Energy Calculation
Rev. PrB | Page 56 of 148
07411-041
Preliminary Technical Data
Figure 45 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are 0x7FF, 0x000, and 0x800. The watt gain register is used to carry out power calibration in the ADE5166/ADE5169/ADE5566/ ADE5569. As shown, the fastest integration time occurs when the watt gain register is set to maximum full scale, that is, 0x7FF.
WATTHR[23:0] 0x7F,FFFF
ADE5166/ADE5169/ADE5566/ADE5569
When WDIV is set to a value other than 0, the integration time varies, as shown in Equation 15. Time = TimeWDIV = 0 x WDIV (15)
Active Energy Accumulation Modes Watt-Signed Accumulation Mode
The ADE5166/ADE5169/ADE5566/ADE5569 active energy default accumulation mode is a watt-signed accumulation based on the active power information.
WGAIN = 0x7FF WGAIN = 0x000 WGAIN = 0x800
Watt Positive-Only Accumulation Mode
The ADE5166/ADE5169/ADE5566/ADE5569 are placed in watt positive-only accumulation mode by setting the POAM bit in the ACCMODE register (0x0F). In this mode, the energy accumulation is only done for positive power, ignoring any occurrence of negative power above or below the no load threshold (see Figure 46). The CF pulse also reflects this accumulation method when in this mode. The default setting for this mode is off. Detection of the transitions in the direction of power flow and detection of no load threshold are active in this mode.
07411-042
0x3F,FFFF
0x00,0000
3.41
6.82
10.2
13.7
TIME (Minutes)
0x40,0000
0x80,0000
Figure 45. Energy Register Rollover Time for Full-Scale Power (Minimum and Maximum Power Gain)
Note that the energy register contents roll over to full-scale negative (0x800000) and continue to increase in value when the power or energy flow is positive (see Figure 45). Conversely, if the power is negative, the energy register underflows to fullscale positive (0x7FFFFF) and continues to decrease in value. By using the interrupt enable register, the ADE5166/ADE5169/ ADE5566/ADE5569 can be configured to issue an ADE interrupt to the 8052 core when the active energy register is half full (positive or negative) or when an overflow or underflow occurs.
ACTIVE ENERGY
NO LOAD THRESHOLD ACTIVE POWER NO LOAD THRESHOLD
Integration Time Under Steady Load: Active Energy
As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 s (5/MLCK). With full-scale sinusoidal signals on the analog inputs and the WGAIN register set to 0x000, the average word value from each LPF2 is 0xCCCCD (see Figure 42). The maximum positive value that can be stored in the internal 49-bit register is 248 (or 0xFFFF,FFFF,FFFF) before it overflows. The integration time under these conditions when WDIV = 0 is calculated in the following equation: Time = 0 xFFFF, FFFF, FFFF x 1.22 s = 409.6 sec = 6.82 min 0 xCCCCD
APSIGN FLAG INTERRUPT STATUS REGISTERS
07411-043
POS
NEG
POS
Figure 46. Energy Accumulation in Positive-Only Accumulation Mode
Watt-Absolute Accumulation Mode
The ADE5166/ADE5169/ADE5566/ADE5569 are placed in watt-absolute accumulation mode by setting the ABSAM bit in the ACCMODE register (0x0F). In this mode, the energy accumulation is done using the absolute active power, ignoring any occurrence of power below the no load threshold (see Figure 47). The CF pulse also reflects this accumulation method when in this mode. The default setting for this mode is off. Detection of the transitions in the direction of power flow, and detection of no load threshold are active in this mode.
(14)
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ADE5166/ADE5169/ADE5566/ADE5569
Preliminary Technical Data
Line Cycle Active Energy Accumulation Mode
In line cycle active energy accumulation mode, the energy accumulation of the ADE5166/ADE5169/ADE5566/ADE5569 can be synchronized to the voltage channel zero crossing so that active energy can be accumulated over an integral number of half-line cycles. The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any ripple in the energy calculation. Energy is calculated more accurately and more quickly because the integration period can be shortened. By using this mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. In the line cycle active energy accumulation mode, the ADE5166/ADE5169/ADE5566/ADE5569 accumulate the active power signal in the LWATTHR register for an integral number of line cycles, as shown in Figure 48. The number of half-line cycles is specified in the LINCYC register. The ADE5166/ADE5169/ADE5566/ADE5569 can accumulate active power for up to 65,535 half-line cycles. Because the active power is integrated on an integral number of line cycles, the CYCEND flag in the Interrupt Status 3 SFR (MIRQSTH, 0xDE) is set at the end of an active energy accumulation line cycle. If the CYCEND enable bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the CYCEND status bit is cleared (see the Energy Measurement Interrupts section). Another calibration cycle starts as soon as the CYCEND flag is set. If the LWATTHR register is not read before a new CYCEND flag is set, the LWATTHR register is overwritten by a new value.
ACTIVE ENERGY
NO LOAD THRESHOLD ACTIVE POWER NO LOAD THRESHOLD
APSIGN FLAG INTERRUPT STATUS REGISTERS
07411-044
APNOLOAD
POS
NEG
POS
APNOLOAD
Figure 47. Energy Accumulation in Absolute Accumulation Mode
Active Energy Pulse Output
All of the ADE5166/ADE5169/ADE5566/ADE5569 circuitry has a pulse output whose frequency is proportional to active power (see the Active Power Calculation section). This pulse frequency output uses the calibrated signal from the WGAIN register output, and its behavior is consistent with the setting of the active energy accumulation mode in the ACCMODE register (0x0F). The pulse output is active low and should be preferably connected to an LED as shown in Figure 58.
TO DIGITAL-TO-FREQUENCY CONVERTER WGAIN[11:0] OUTPUT FROM LPF2 WATTOS[15:0] + + 48 0
%
WDIV[7:0] ACCUMULATE ACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE THE LWATTHR REGISTER AT THE END OF LINCYC HALF-LINE CYCLES
LPF1 FROM VOLTAGE CHANNEL ADC ZERO-CROSSING DETECTION CALIBRATION CONTROL
23
LWATTHR[23:0]
0
LINCYC[15:0]
Figure 48. Line Cycle Active Energy Accumulation
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07411-046
Preliminary Technical Data
When a new half-line cycle is written in the LINCYC register, the LWATTHR register is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached. This implementation provides a valid measurement at the first CYCEND interrupt after writing to the LINCYC register (see Figure 49). The line active energy accumulation uses the same signal path as the active energy accumulation. The LSB size of these two registers is equivalent.
ADE5166/ADE5169/ADE5566/ADE5569
v(t ) = 2 V sin(t + ) i(t ) = 2 I sin(t ) i (t ) = 2 I sin t + 2 (20) (19)
where: is the phase difference between the voltage and current channel. v is the rms voltage. i is the rms current. q(t) = v(t) x i'(t) q(t) = VI sin () + VI sin(2t + ) (21)
LWATTHR REGISTER
CYCEND IRQ
07411-045
The average reactive power over an integral number of lines (n) is given in Equation 22. Q= 1 nT
nT 0
LINCYC VALUE
q(t )dt = VI sin()
(22)
Figure 49. Energy Accumulation When LINCYC Changes
From the information in Equation 8 and Equation 9,
nT nT VI E (t ) = VIdt - cos(2ft )dt 2 0 f 0 1+ 8.9 where: n is an integer. T is the line cycle period.
where: T is the line cycle period. q is referred to as the reactive power.
(16)
Note that the reactive power is equal to the dc component of the instantaneous reactive power signal q(t) in Equation 21. The instantaneous reactive power signal q(t) is generated by multiplying the voltage and current channels. In this case, the phase of the current channel is shifted by 90. The dc component of the instantaneous reactive power signal is then extracted by a low-pass filter to obtain the reactive power information (see Figure 50). In addition, the phase-shifting filter has a nonunity magnitude response. Because the phase-shifted filter has a large attenuation at high frequency, the reactive power is primarily for calculation at line frequency. The effect of harmonics is largely ignored in the reactive power calculation. Note that, because of the magnitude characteristic of the phase shifting filter, the weight of the reactive power is slightly different from the active power calculation (see the Energy Register Scaling section). The frequency response of the LPF in the reactive signal path is identical to the one used for LPF2 in the average active power calculation. Because LPF2 does not have an ideal brick wall frequency response (see Figure 43), the reactive power signal has some ripple due to the instantaneous reactive power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the reactive power signal is integrated to calculate energy. The reactive power signal can be read from the waveform register by setting the WAVMODE register (0x0D) and the WFSM bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB). Like the current and voltage channels waveform sampling modes, the waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS.
Because the sinusoidal component is integrated over an integer number of line cycles, its value is always 0. Therefore,
E = VIdt + 0
0
nT
(17) (18)
E(t) = VInT
Note that in this mode, the 16-bit LINCYC register can hold a maximum value of 65,535. In other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration of over 65,535 half-line cycles. At a 60 Hz line frequency, it translates to a total duration of 65,535/120 Hz = 546 sec.
REACTIVE POWER CALCULATION FOR THE ADE5569/ADE5169
Reactive power, a function available for the ADE5569/ADE5169 but not for the ADE5566/ADE5166, is defined as the product of the voltage and current waveforms when one of these signals is phase-shifted by 90. The resulting waveform is called the instantaneous reactive power signal. Equation 21 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by 90.
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ADE5166/ADE5169/ADE5566/ADE5569
Reactive Power Gain Calibration
Figure 50 shows the signal processing chain for the ADE5569/ ADE5169 reactive power calculation. As explained in the Reactive Power Calculation for the ADE5569/ADE5169 section, the reactive power is calculated by applying a low-pass filter to the instantaneous reactive power signal. Note that, when reading the waveform samples from the output of LPF2, the gain of the reactive energy can be adjusted by using the multiplier and by writing a twos complement, 12-bit word to the VAR gain register (VARGAIN[11:0]). Equation 23 shows how the gain adjustment is related to the contents of the watt gain register. Output VARGAIN =
Preliminary Technical Data
(MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the VARSIGN status bit is cleared (see the Energy Measurement Interrupts section). When VARSIGN in the ACCMODE register (0x0F) is cleared (default), the VARSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set when a transition from positive to negative reactive power occurs. When VARSIGN in the ACCMODE register (0x0F) is set, the VARSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set when a transition from negative to positive reactive power occurs.
Reactive Power No Load Detection
The ADE5569/ADE5169 include a no load threshold feature on the reactive energy that eliminates any creep effects in the meter. The ADE5569/ADE5169 accomplish this by not accumulating reactive energy when the multiplier output is below the no load threshold. When the reactive power is below the no load threshold, the RNOLOAD flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set. If the RNOLOAD bit is set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the RNOLOAD status bit is cleared (see the Energy Measurement Interrupts section). The no load threshold level is selectable by setting the VARNOLOAD bits in the NLMODE register (0x0E). Setting these bits to 0b00 disables the no load detection, and setting them to 0b01, 0b10, or 0b11 sets the no load detection threshold to 0.015%, 0.0075%, and 0.0037% of the full-scale output frequency of the multiplier, respectively.
VARGAIN Reactive Power x 1 + 212
The resolution of the VARGAIN register is the same as the WGAIN register (see the Active Power Gain Calibration section). VARGAIN can be used to calibrate the reactive power (or energy) calculation in the ADE5569/ADE5169.
(23)
Reactive Power Offset Calibration
The ADE5569/ADE5169 also incorporate a reactive power offset register (VAROS[15:0]). This is a signed, twos complement, 16-bit register that can be used to remove offsets in the reactive power calculation (see Figure 50). An offset can exist in the reactive power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the reactive power register to be maintained at 0 when no power is being consumed. The 256 LSBs (VAROS = 0x100) written to the reactive power offset register are equivalent to 1 LSB in the WAVMODE register.
Sign of Reactive Power Calculation
Note that the average reactive power is a signed calculation. The phase shift filter has -90 phase shift when the integrator is enabled, and +90 phase shift when the integrator is disabled. Table 46 summarizes the relationship of the phase difference between the voltage and the current and the sign of the resulting VAR calculation.
Table 46. Sign of Reactive Power Calculation
Angle Between 0 to +90 Between -90 to 0 Between 0 to +90 Between -90 to 0 Integrator Off Off On On Sign Positive Negative Positive Negative
REACTIVE ENERGY CALCULATION FOR THE ADE5569/ADE5169
As for active energy, the ADE5569/ADE5169 achieve the integration of the reactive power signal by continuously accumulating the reactive power signal in an internal, nonreadable, 49-bit energy register. The reactive energy register (VARHR[23:0]) represents the upper 24 bits of this internal register. The VARHR register and its function are available for the ADE5569/ADE5169 but not for the ADE5566/ADE5166. The discrete time sample period (T) for the accumulation register in the ADE5569/ADE5169 is 1.22 s (5/MCLK). As well as calculating the energy, this integration removes any sinusoidal components that may be in the active power signal. Figure 50 shows this discrete time integration or accumulation. The reactive power signal in the waveform register is continuously added to the internal reactive energy register. The reactive energy accumulation depends on the setting of the SAVARM and ABSVARM bits in the ACCMODE register (0x0F). When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the reactive energy contents. When both bits are set, the ADE5569/ADE5169 are set to be in the more restrictive mode, the absolute accumulation mode.
Reactive Power Sign Detection
The ADE5569/ADE5169 detect a change of sign in the reactive power. The VARSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) records when a change of sign has occurred according to the VARSIGN bit in the ACCMODE register (0x0F). If the VARSIGN bit is set in the Interrupt Enable 1 SFR
Rev. PrB | Page 60 of 148
Preliminary Technical Data
When SAVARM in the ACCMODE register (0x0F) is set, the reactive power is accumulated depending on the sign of the active power. When active power is positive, the reactive power is added as it is to the reactive energy register. When active power is negative, the reactive power is subtracted from the reactive energy accumulator (see the VAR Antitamper Accumulation Mode section). When ABSVARM in the ACCMODE register (0x0F) is set, the absolute reactive power is used for the reactive energy accumulation (see the VAR Absolute Accumulation Mode section). The output of the multiplier is divided by VARDIV. If the value in the VARDIV register is equal to 0, the internal reactive energy register is divided by 1. VARDIV is an 8-bit, unsigned register. After dividing by VARDIV, the reactive energy is accumulated in a 49-bit internal energy accumulation register. The upper 24 bits of this register are accessible through a read to the reactive energy register (VARHR[23:0]). A read to the RVARHR register returns the content of the VARHR register, and the upper 24 bits of the internal register are cleared.
ADE5166/ADE5169/ADE5566/ADE5569
As shown in Figure 50, the reactive power signal is accumulated in an internal 49-bit signed register. The reactive power signal can be read from the waveform register by setting the WAVMODE register (0x0D) and setting the WFSM bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB). Like the current and voltage channel waveform sampling modes, the waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. Figure 45 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. These curves also apply for the reactive energy accumulation. Note that the energy register contents roll over to full-scale negative (0x800000) and continue to increase in value when the power or energy flow is positive. Conversely, if the power is negative, the energy register underflows to full-scale positive (0x7FFFFF) and continues to decrease in value. By using the interrupt enable register, the ADE5569/ADE5169 can be configured to issue an ADE interrupt to the 8052 core when the reactive energy register is half-full (positive or negative) or when an overflow or underflow occurs.
UPPER 24 BITS ARE ACCESSIBLE THROUGH VARHR[23:0] REGISTER 0
FOR WAVEFORM SAMPLING 90 PHASE SHIFTING FILTER 2 VAROS[15:0] sgn 26 25 LPF2 + VOLTAGE CHANNEL + 2-6 2-7 2-8
23
VARHR[23:0]
CURRENT CHANNEL
HPF
VARDIV[7:0] + +
48 0
%
PHCAL[7:0] REACTIVE POWER SIGNAL
VARGAIN[11:0] OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL REACTIVE ENERGY REGISTER
TO DIGITAL-TO-FREQUENCY CONVERTER T 5 MCLK WAVEFORM REGISTER VALUES
OUTPUT LPF2
TIME (nT)
Figure 50. Reactive Energy Calculation
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Integration Time Under Steady Load: Reactive Energy
As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 s (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the VARGAIN and VARDIV registers set to 0x000, the integration time before the reactive energy register overflows is calculated in Equation 24. Time = 0xFFFF, FFFF, FFFF x 1.22 s = 409.6 sec = 6.82 min (24) 0xCCCCD When VARDIV is set to a value different from 0, the integration time varies, as shown in Equation 25. Time = TimeWDIV =0 x VARDIV (25)
Preliminary Technical Data
REACTIVE ENERGY
NO LOAD THRESHOLD
REACTIVE POWER NO LOAD THRESHOLD
Reactive Energy Accumulation Modes VAR Signed Accumulation Mode
The ADE5569/ADE5169 reactive energy default accumulation mode is a signed accumulation based on the reactive power information.
NO LOAD THRESHOLD
ACTIVE POWER NO LOAD THRESHOLD
VAR Antitamper Accumulation Mode
The ADE5569/ADE5169 are placed in VAR antitamper accumulation mode by setting the SAVARM bit in the ACCMODE register (0x0F). In this mode, the reactive power is accumulated depending on the sign of the active power. When active power is positive, the reactive power is added as it is to the reactive energy register. When active power is negative, the reactive power is subtracted from the reactive energy accumulator (see Figure 51). The CF pulse also reflects this accumulation method when in this mode. The default setting for this mode is off. Transitions in the direction of power flow and no load threshold are active in this mode.
APSIGN FLAG POS NEG POS INTERRUPT STATUS REGISTERS
07411-048
Figure 51. Reactive Energy Accumulation in Antitamper Accumulation Mode
Rev. PrB | Page 62 of 148
Preliminary Technical Data
VAR Absolute Accumulation Mode
The ADE5569/ADE5169 are placed in absolute accumulation mode by setting the ABSVARM bit in the ACCMODE register (0x0F). In absolute accumulation mode, the reactive energy accumulation is done by using the absolute reactive power and ignoring any occurrence of power below the no load threshold for the active energy (see Figure 47). The CF pulse also reflects this accumulation method when in the absolute accumulation mode. The default setting for this mode is off. Transitions in the direction of power flow and no load threshold are active in this mode.
ADE5166/ADE5169/ADE5566/ADE5569
Line Cycle Reactive Energy Accumulation Mode
In line cycle reactive energy accumulation mode, the energy accumulation of the ADE5569/ADE5169 can be synchronized to the voltage channel zero crossing so that reactive energy can be accumulated over an integral number of half-line cycles. The advantage of this mode is similar to the ones described in the Line Cycle Active Energy Accumulation Mode section. In line cycle active energy accumulation mode, the ADE5569/ ADE5169 accumulate the reactive power signal in the LVARHR register for an integral number of line cycles, as shown in Figure 53. The number of half-line cycles is specified in the LINCYC register. The ADE5569/ADE5169 can accumulate active power for up to 65,535 half-line cycles. Because the reactive power is integrated on an integral number of line cycles, the CYCEND flag in the Interrupt Status 3 SFR (MIRQSTH, 0xDE) is set at the end of an active energy accumulation line cycle. If the CYCEND enable bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the CYCEND status bit is cleared (see the Energy Measurement Interrupts section). Another calibration cycle starts as soon as the CYCEND flag is set. If the LVARHR register is not read before a new CYCEND flag is set, the LVARHR register is overwritten by a new value. When a new half-line cycle is written in the LINECYC register, the LVARHR register is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached. This implementation provides a valid measurement at the first CYCEND interrupt after writing to the LINCYC register. The line reactive energy accumulation uses the same signal path as the reactive energy accumulation. The LSB size of these two registers is equivalent.
REACTIVE ENERGY
NO LOAD THRESHOLD REACTIVE POWER NO LOAD THRESHOLD
07411-049
Figure 52. Reactive Energy Accumulation in Absolute Accumulation Mode
Reactive Energy Pulse Output
The ADE5569/ADE5169 provide all the circuitry with a pulse output whose frequency is proportional to reactive power (see the Energy-to-Frequency Conversion section). This pulse frequency output uses the calibrated signal after VARGAIN, and its behavior is consistent with the setting of the reactive energy accumulation mode in the ACCMODE register (0x0F). The pulse output is active low and should preferably be connected to an LED, as shown in Figure 58.
TO DIGITAL-TO-FREQUENCY CONVERTER VARGAIN[11:0] OUTPUT FROM LPF2 VAROS[15:0]
%
+
+
48
0
VARDIV[7:0] ACCUMULATE REACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE THE LVARHR REGISTER AT THE END OF LINCYC HALF-LINE CYCLES
LPF1 FROM VOLTAGE CHANNEL ADC
23 ZERO-CROSSING DETECTION
CALIBRATION CONTROL LVARHR[23:0]
0
LINCYC[15:0]
Figure 53. Line Cycle Reactive Energy Accumulation Mode
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ADE5166/ADE5169/ADE5566/ADE5569
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be delivered to a load. Vrms and Irms are the effective voltage and current delivered to the load, respectively. Therefore, the apparent power (AP) = Vrms x Irms. This equation is independent from the phase angle between the current and the voltage. Equation 29 gives an expression of the instantaneous power signal in an ac system with a phase shift.
v(t ) = 2 Vrms sin( t )
Preliminary Technical Data
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value (see the Current Channel RMS Calculation section and the Voltage Channel RMS Calculation section). The voltage and current channels rms values are then multiplied together in the apparent power signal processing. Because no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement is done by calibrating each individual rms measurement.
(26) (27) (29) (30)
i (t ) = 2 I rms sin(t + )
p (t ) = v (t ) x i (t )
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent power.
Apparent Energy = Apparent Power(t )dt
p(t ) = Vrms I rms cos() - Vrms I rms cos(2t + )
Figure 54 illustrates the signal processing for the calculation of the apparent power in the ADE5166/ADE5169/ADE5566/ADE5569. The apparent power signal can be read from the waveform register by setting the WAVMODE register (0x0D) and setting the WFSM bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB). Like the current and voltage channel waveform sampling modes, the waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. The gain of the apparent energy can be adjusted by using the multiplier and by writing a twos complement, 12-bit word to the VAGAIN register (VAGAIN[11:0]). Equation 30 shows how the gain adjustment is related to the contents of the VAGAIN register. Output VAGAIN =
VAGAIN Apparent Power x 1 + 2 12
(31)
The ADE5166/ADE5169/ADE5566/ADE5569 achieve the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. The apparent energy register (VAHR[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 32 expresses the relationship.
Apparent Energy = lim Apparent Power ( nT ) x T (32) T 0 n=0
where: n is the discrete time sample number. T is the sample period.
(30)
For example, when 0x7FF is written to the VAGAIN register, the power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5). Similarly, 0x800 = -2047d (signed twos complement) and power output is scaled by -50%. Each LSB represents 0.0244% of the power output. The apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ADE5166/ADE5169/ADE5566/ADE5569.
VARMSCFCON APPARENT POWER SIGNAL (P)
Irms
CURRENT RMS SIGNAL - i(t) 0x1CF68C 0x00
0x1A36E2
VAGAIN Vrms
VOLTAGE RMS SIGNAL - v(t)
0x1CF68C 0x00
Figure 54. Apparent Power Signal Processing
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07411-051
TO DIGITAL-TO-FREQUENCY CONVERTER
Preliminary Technical Data
The discrete time sample period (T) for the accumulation register in the ADE5166/ADE5169/ADE5566/ADE5569 is 1.22 s (5/MCLK). Figure 55 shows this discrete time integration or accumulation. The apparent power signal is continuously added to the internal register. This addition is a signed addition even if the apparent energy theoretically remains positive. The 49 bits of the internal register are divided by VADIV. If the value in the VADIV register is 0, the internal apparent energy register is divided by 1. VADIV is an 8-bit unsigned register. The upper 24 bits are then written in the 24-bit apparent energy register (VAHR[23:0]). The RVAHR register (24 bits long) is provided to read the apparent energy. This register is reset to 0 after a read operation Note that the apparent energy register is unsigned. By setting the VAEHF and VAEOF bits in the Interrupt Enable 2 SFR (MIRQENM, 0xDA), the ADE5166/ADE5169/ADE5566/ ADE5569 can be configured to issue an ADE interrupt to the 8052 core when the apparent energy register is half-full or when an overflow occurs. The half-full interrupt for the unsigned apparent energy register is based on 24 bits as opposed to 23 bits for the signed active energy register.
ADE5166/ADE5169/ADE5566/ADE5569
analog inputs and the VAGAIN register set to 0x000, the average word value from the apparent power stage is 0x1A36E2 (see the Apparent Power Calculation section). The maximum value that can be stored in the apparent energy register before it overflows is 224 or 0xFF,FFFF. The average word value is added to the internal register, which can store 248 or 0xFFFF,FFFF,FFFF before it overflows. Therefore, the integration time under these conditions with VADIV = 0 is calculated as follows: Time = 0xFFFF, FFFF, FFFF x 1.22 s = 199 sec = 3.33 min 0xD055
(33)
When VADIV is set to a value different from 0, the integration time varies, as shown in Equation 34. Time = TimeWDIV = 0 x VADIV (34)
Apparent Energy Pulse Output
All the ADE5166/ADE5169/ADE5566/ADE5569 circuitry has a pulse output whose frequency is proportional to apparent power (see the Energy-to-Frequency Conversion section). This pulse frequency output uses the calibrated signal after VAGAIN. This output can also be used to output a pulse whose frequency is proportional to Irms. The pulse output is active low and should preferably be connected to an LED, as shown in Figure 58.
Integration Times Under Steady Load: Apparent Energy
As mentioned in the Apparent Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 s (5/MCLK). With full-scale sinusoidal signals on the
23
VAHR[23:0]
0
48
0
VADIV
%
APPARENT POWER or Irms
+ +
48
0
APPARENT POWER SIGNAL = P T
APPARENT POWER OR Irms IS ACCUMULATED (INTEGRATED) IN THE APPARENT ENERGY REGISTER
TIME (nT)
Figure 55. Apparent Energy Calculation
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ADE5166/ADE5169/ADE5566/ADE5569
Line Apparent Energy Accumulation
The ADE5166/ADE5169/ADE5566/ADE5569 are designed with a special apparent energy accumulation mode that simplifies the calibration process. By using the on-chip, zerocrossing detection, the ADE5166/ADE5169/ADE5566/ADE5569 accumulate the apparent power signal in the LVAHR register for an integral number of half cycles, as shown in Figure 56. The line apparent energy accumulation mode is always active. The number of half-line cycles is specified in the LINCYC register, which is an unsigned 16-bit register. The ADE5166/ ADE5169/ADE5566/ADE5569 can accumulate apparent power for up to 65,535 combined half cycles. Because the apparent power is integrated on the same integral number of line cycles as the line active register and reactive energy register, these values can easily be compared. The energies are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation. At the end of an energy calibration cycle, the CYCEND flag in the Interrupt Status 3 SFR (MIRQSTH, 0xDE) is set. If the CYCEND enable bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB) is enabled, the 8052 core has a pending ADE interrupt. As for LWATTHR, when a new half-line cycles is written in LINCYC register, the LVAHR register is reset and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached. This implementation provides a valid measurement at the first CYCEND interrupt after writing to the LINCYC register. The line apparent energy accumulation uses the same signal path as the apparent energy accumulation. The LSB size of these two registers is equivalent.
Preliminary Technical Data
If the VANOLOAD bit is set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APNOLOAD status bit is cleared (see the Energy Measurement Interrupts section). The no load threshold level is selectable by setting the VANOLOAD bits in the NLMODE register (0x0E). Setting these bits to 0b00 disables the no load detection and setting them to 0b01, 0b10, or 0b11 sets the no load detection threshold to 0.030%, 0.015%, and 0.0075% of the full-scale output frequency of the multiplier, respectively. This no load threshold can also be applied to the Irms pulse output when selected. In this case, the level of no load threshold is the same as for the apparent energy.
AMPERE-HOUR ACCUMULATION
In a tampering situation where no voltage is available to the energy meter, the ADE5166/ADE5169/ADE5566/ADE5569 is capable of accumulating the ampere-hour instead of apparent power into the VAHR, RVAHR, and LVAHR. When Bit 3 (VARMSCFCON) of the MODE2 register (0x0C) is set, the VAHR, RVAHR, and LVAHR, and the input for the digital-tofrequency converter accumulate Irms instead of apparent power. All the signal processing and calibration registers available for apparent power and energy accumulation remain the same when ampere-hour accumulation is selected. However, the scaling difference between Irms and apparent power requires independent values for gain calibration in the VAGAIN, VADIV, CFxNUM, and CFxDEN registers.
ENERGY-TO-FREQUENCY CONVERSION
The ADE5166/ADE5169/ADE5566/ADE5569 also provide two energy-to-frequency conversions for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verifies the energy meter calibration. One convenient way to do this is for the manufacturer to provide an output frequency that is proportional to the active power, reactive power, apparent power, or Irms under steady load conditions. This output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 57 illustrates the energy-to-frequency conversion in the ADE5166/ ADE5169/ADE5566/ADE5569.
+ + 48 0
Apparent Power No Load Detection
The ADE5166/ADE5169/ADE5566/ADE5569 include a no load threshold feature on the apparent power that eliminates any creep effects in the meter. The ADE5166/ADE5169/ADE5566/ ADE5569 accomplish this by not accumulating energy if the multiplier output is below the no load threshold. When the apparent power is below the no load threshold, the VANOLOAD flag in the Interrupt Status 1 SFR (MIRQSTL, 0xDC) is set.
APPARENT POWER OR Irms
%
VADIV[7:0]
LVAHR REGISTER IS UPDATED EVERY LINCYC ZERO CROSSING WITH THE TOTAL APPARENT ENERGY DURING THAT DURATION 23 0 LVAHR[23:0]
LPF1 FROM VOLTAGE CHANNEL ADC
ZERO-CROSSING DETECTION
CALIBRATION CONTROL
LINCYC[15:0]
Figure 56. Line Cycle Apparent Energy Accumulation
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Preliminary Technical Data
MODE2 REGISTER 0x0C VARMSCFCON CFxSEL[1:0]
ADE5166/ADE5169/ADE5566/ADE5569
VDD CF
Irms
VA VAR* WATT DFC
CFxNUM
/
CFxDEN
CFx PULSE OUTPUT
07411-054
Figure 58. CF Pulse Output
The maximum output frequency with ac input signals at full scale and CFxNUM = 0x00 and CFxDEN = 0x00 is approximately 21.1 kHz. The ADE5166/ADE5169/ADE5566/ADE5569 incorporate two registers per DFC, CFxNUM[15:0] and CFxDEN[15:0], to set the CFx frequency. These are unsigned 16-bit registers that can be used to adjust the CFx frequency to a wide range of values. These frequency scaling registers are 16-bit registers that can scale the output frequency by 1/216 to 1 with a step of 1/216. If 0 is written to any of these registers, 1 is applied to the register. The ratio CFxNUM/CFxDEN should be less than 1 to ensure proper operation. If the ratio of the CFxNUM/CFxDEN registers is greater than 1, the register values are adjusted to a ratio of 1. For example, if the output frequency is 1.562 kHz while the content of CFxDEN is 0 (0x000), the output frequency can be set to 6.1 Hz by writing 0xFF to the CFxDEN register.
*AVAILABLE ONLY IN THE ADE5569 AND ADE5169.
Figure 57. Energy-to-Frequency Conversion
Two digital-to-frequency converters (DFC) are used to generate the pulsed outputs. When WDIV = 0 or 1, the DFC generates a pulse each time 1 LSB in the energy register is accumulated. An output pulse is generated when a CFxNUM/CFxDEN number of pulses are generated at the DFC output. Under steady load conditions, the output frequency is proportional to the active power, reactive power, apparent power, or Irms, depending on the CFxSEL bits in the MODE2 register (0x0C). Both pulse outputs can be enabled or disabled by clearing or setting Bit DISCF1 and Bit DISCF2 in the MODE1 register (0x0B), respectively. Both pulse outputs set separate flags in the Interrupt Status 2 SFR (MIRQSTM, 0xDD), CF1 and CF2. If the CF1 and CF2 enable bits in the Interrupt Enable 2 SFR (MIRQENM, 0xDA) are set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the CF1 or CF2 status bits are cleared (see the Energy Measurement Interrupts section).
ENERGY REGISTER SCALING
The ADE5166/ADE5169/ADE5566/ADE5569 provide measurements of active, reactive, and apparent energies that use separate paths and filtering for calculation. The difference in data paths can result in small differences in LSB weight between active, reactive, and apparent energy registers. These measurements are internally compensated so the scaling is nearly one to one. The relationship between these registers is shown in Table 47.
Table 47. Energy Registers Scaling
Line Frequency = 50 Hz VAR = 0.9952 x WATT VA = 0.9978 x WATT VAR = 0.9997 x WATT VA = 0.9977 x WATT Line Frequency = 60 Hz VAR = 0.9949 x WATT VA = 1.0015 x WATT VAR = 0.9999 x WATT VA = 1.0015 x WATT Integrator Off Off On On
Pulse Output Configuration
The two pulse output circuits have separate configuration bits in the MODE2 Register (0x0C). Setting the CFxSEL bits to 0b00, 0b01, or 0b1x configures the DFC to create a pulse output proportional to active power, to reactive power (not available in the ADE5566 and ADE5166), or to apparent power or Irms, respectively. The selection between Irms and apparent power is done by the VARMSCFCON bit in the MODE2 register (0x0C). With this selection, CF2 cannot be proportional to apparent power if CF1 is proportional to Irms, and CF1 cannot be proportional to apparent power if CF2 is proportional to Irms.
ENERGY MEASUREMENT INTERRUPTS
The energy measurement part of the ADE5166/ADE5169/ ADE5566/ADE5569 has its own interrupt vector for the 8052 core, Vector Address 0x004B (see the Interrupt Vectors section). The bits set in the Interrupt Enable 1 SFR (MIRQENL, 0xD9), Interrupt Enable 2 SFR (MIRQENM, 0xDA), and Interrupt Enable 3 SFR (MIRQENH, 0xDB) enable the energy measurement interrupts that are allowed to interrupt the 8052 core. If an event is not enabled, it cannot create a system interrupt. The ADE interrupt stays active until the status bit that has created the interrupt is cleared. The status bit is cleared when a zero is written to this register bit.
Pulse Output Characteristic
The pulse output for both DFCs stays low for 90 ms if the pulse period is longer than 180 ms (5.56 Hz). If the pulse period is shorter than 180 ms, the duty cycle of the pulse output is 50%. The pulse output is active low and should preferably be connected to an LED, as shown in Figure 58.
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ADE5166/ADE5169/ADE5566/ADE5569
The ADE5166/ADE5169/ADE5566/ADE5569 include temperature measurements as well as battery and supply voltage measurements. These measurements enable many forms of compensation. The temperature and supply voltage measurements can be used to compensate external circuitry. The RTC can be calibrated over temperature to ensure that it does not drift. Supply voltage measurements allow the LCD contrast to be maintained despite variations in voltage. Battery measurements allow low battery detection to be performed.
Preliminary Technical Data
All ADC measurements are configured through the SFRs detailed in Table 48. The temperature, battery, and supply voltage measurements can be configured to continue functioning in PSM1 and PSM2. Keeping the temperature measurement active ensures that it is not necessary to wait for the temperature measurement to settle before using it for compensation.
TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS
Table 48. Temperature, Battery, and Supply Voltage Measurement SFRs
SFR Address 0xF9 0xF3 0xD8 0xFA 0xEF 0xDF 0xD7 R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic STRBPER DIFFPROG ADCGO BATVTH VDCINADC BATADC TEMPADC Description Peripheral ADC Strobe Period (see Table 49). Temperature and Supply Delta Configuration (see Table 50). Start ADC Measurement (see Table 51). Battery Detection Threshold (see Table 52). VDCIN ADC Value (see Table 53). Battery ADC Value (see Table 54). Temperature ADC Value (see Table 55).
Table 49. Peripheral ADC Strobe Period SFR (STRBPER, 0xF9)
Bit 7 to 6 5 to 4 Mnemonic Reserved VDCIN_PERIOD[1:0] Default 00 0 Description These bits should be left clear for proper operation. Period for background external voltage measurements. VDCIN_PERIOD[1:0] Result 00 No VDCIN measurement 01 8 min 10 2 min 11 1 min Period for background battery level measurements. BATT_PERIOD[1:0] Result 00 No battery measurement 01 16 min 10 4 min 11 1 min Period for background temperature measurements. TEMP_PERIOD[1:0] Result 00 No temperature measurements 01 8 min 10 2 min 11 1 min
3 to 2
BATT_PERIOD[1:0]
0
1 to 0
TEMP_PERIOD[1:0]
0
Rev. PrB | Page 68 of 148
Preliminary Technical Data
Table 50. Temperature and Supply Delta SFR (DIFFPROG, 0xF3)
Bit 7 to 6 5 to 3 Mnemonic Reserved TEMP_DIFF[2:0] Default 0 0
ADE5166/ADE5169/ADE5566/ADE5569
2 to 0
VDCIN_DIFF[2:0]
0
Description Reserved. Difference threshold between last temperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052. TEMP_DIFF[2:0] Result 000 No interrupt 001 1 LSB ( 0.8C) 010 2 LSB ( 1.6C) 011 3 LSB ( 2.4C) 100 4 LSB ( 3.2C) 101 5 LSB ( 4C) 110 6 LSB ( 4.8C) 111 Every temperature measurement Difference threshold between last external voltage measurement interrupting 8052 and new external measurement that should interrupt 8052. VDCIN_DIFF[2:0] Result 000 No interrupt 001 1 LSB ( 120 mV) 010 2 LSB ( 240 mV) 011 3 LSB ( 360 mV) 100 4 LSB ( 480 mV) 101 5 LSB ( 600 mV) 110 6 LSB ( 720 mV) 111 Every VDCIN measurement
Table 51. Start ADC Measurement SFR (ADCGO, 0xD8)
Bit 7 6 to 3 2 1 0 Address 0xDF 0xDE to 0xDB 0xDA 0xD9 0xD8 Mnemonic PLLACK Reserved VDCIN_ADC_GO TEMP_ADC_GO BATT_ADC_GO Default 0 0 0 0 0 Description Set this bit to clear the PLL fault bit, PLL_FLT, in the PERIPH register. A PLL fault is generated if a reset is caused because the PLL lost lock. Reserved. Set this bit to initiate an external voltage measurement. This bit is cleared when the measurement request is received by the ADC. Set this bit to initiate a temperature measurement. This bit is cleared when the measurement request is received by the ADC. Set this bit to initiate a battery measurement. This bit is cleared when the measurement request is received by the ADC.
Table 52. Battery Detection Threshold SFR (BATVTH, 0xFA)
Bit 7 to 0 Mnemonic BATVTH Default 0 Description The battery ADC value is compared to this register, the battery threshold register. If BATADC is lower than the threshold, an interrupt is generated.
Table 53. VDCIN ADC Value SFR (VDCINADC, 0xEF)
Bit 7 to 0 Mnemonic VDCINADC Default 0 Description The VDCIN ADC value in this register is updated when an ADC interrupt occurs.
Table 54. Battery ADC Value SFR (BATADC, 0xDF)
Bit 7 to 0 Mnemonic BATADC Default 0 Description The battery ADC value in this register is updated when an ADC interrupt occurs.
Table 55. Temperature ADC Value SFR (TEMPADC, 0xD7)
Bit 7 to 0 Mnemonic TEMPADC Default 0 Description The temperature ADC value in this register is updated when an ADC interrupt occurs.
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ADE5166/ADE5169/ADE5566/ADE5569
TEMPERATURE MEASUREMENT
To provide a digital temperature measurement, each ADE5166/ ADE5169/ADE5566/ADE5569 includes a dedicated ADC. An 8-bit temperature ADC value SFR (TEMPADC, 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.78C/LSB. There are two ways to initiate a temperature conversion: a single temperature measurement or background temperature measurements. *
Preliminary Technical Data
start ADC measurement SFR (ADCGO, 0xD8). Background temperature measurements are not available. In PSM2 operating mode, the 8052 is not active. Temperature conversions are available through the background measurement mode only.
The temperature ADC value SFR (TEMPADC, 0xD7) is updated with a new value only when a temperature ADC interrupt occurs.
Temperature ADC Interrupt
The temperature ADC can generate an ADC interrupt when at least one of the following conditions occurs: * The difference between the new temperature ADC value and the last temperature ADC value generating an ADC interrupt is larger than the value set in the TEMP_DIFF[2:0] bits. The temperature ADC conversion, initiated by setting start ADC measurement SFR (ADCGO, 0xD8) finishes.
Single Temperature Measurement
Set the TEMP_ADC_GO bit in the start ADC measurement SFR (ADCGO, 0xD8) to obtain a temperature measurement (see Table 51). An interrupt is generated when the conversion is complete and when the temperature measurement is available in the temperature ADC value SFR (TEMPADC, 0xD7).
Background Temperature Measurements
Background temperature measurements are disabled by default. To configure the background temperature measurement mode, set a temperature measurement interval in the peripheral ADC strobe period SFR (STRBPER, 0xF9). Temperature measurements are then performed periodically in the background (see Table 49). When a temperature conversion completes, the new temperature ADC value is compared to the last temperature ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting in the TEMP_DIFF[2:0] bits in the temperature and supply delta SFR (DIFFPROG, 0xF3), a TEMPADC interrupt is generated (see Table 50). This allows temperature measurements to take place completely in the background, only requiring MCU activity if the temperature changes more than a configurable delta. To set up background temperature measurements, follow these steps: 1. Initiate a single temperature measurement by setting the TEMP_ADC_GO bit in the start ADC measurement SFR (ADCGO, 0xD8). Upon completion of this measurement, configure the TEMP_DIFF[2:0] bits to establish the change in temperature that triggers an interrupt. Set up the interval for background temperature measurements by configuring the TEMP_PERIOD[1:0] bits in the peripheral ADC strobe period SFR (STRBPER, 0xF9).
*
When the ADC interrupt occurs, a new value is available in the temperature ADC value SFR (TEMPADC, 0xD7). Note that there is no flag associated with this interrupt.
BATTERY MEASUREMENT
To provide a digital battery measurement, each ADE5166/ ADE5169/ADE5566/ADE5569 includes a dedicated ADC. The battery measurement is available in an 8-bit SFR, the battery ADC value SFR (BATADC, 0xDF). The battery measurement has a resolution of 14.6 mV/LSB. A battery conversion can be initiated by two methods: a single battery measurement or background battery measurements.
Single Battery Measurement
Set the BATT_ADC_GO bit in the start ADC measurement SFR (ADCGO, 0xD8) to obtain a battery measurement. An interrupt is generated when the conversion is done and when the battery measurement is available in the battery ADC value SFR (BATADC, 0xDF).
Background Battery Measurements
To configure background measurements for the battery, establish a measurement interval in the peripheral ADC strobe period SFR (STRBPER, 0xF9). Battery measurements are then performed periodically in the background (see Table 49). When a battery conversion completes, the battery ADC value is compared to the low battery threshold, established in the battery detection threshold SFR (BATVTH, 0xFA). If the battery ADC value is below this threshold, a low battery flag is set. This low battery flag is the FBAT bit in the power management interrupt flag SFR (IPSMF, 0xF8), which is used for power supply management. This low battery flag can be enabled to generate the PSM interrupt by setting the EBAT bit in the power management interrupt enable SFR (IPSME, 0xEC). This method allows battery measurements to take place completely in the background, only requiring MCU activity if the battery drops below a user-specified threshold.
2.
3.
Temperature ADC in PSM0, PSM1, and PSM2
Depending on the operating mode of the ADE5166/ADE5169/ ADE5566/ADE5569, a temperature conversion is initiated only by certain actions. * In PSM0 operating mode, the 8052 is active. Temperature measurements are available in the background measurement mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is battery powered. Single temperature measurements can be initiated by setting the TEMP_ADC_GO bit in the
*
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Preliminary Technical Data
To set up background battery measurements, follow these steps: 1. Configure the battery detection threshold SFR (BATVTH, 0xFA) to establish a low battery threshold. If the BATADC measurement is below this threshold, the FBAT in the power management interrupt flag SFR (IPSMF, 0xF8) is set. Set up the interval for background battery measurements by configuring the BATT_PERIOD[1:0] bits in the peripheral ADC strobe period SFR (STRBPER, 0xF9).
ADE5166/ADE5169/ADE5566/ADE5569
Single External Voltage Measurement
To obtain an external voltage measurement, set the VDCIN_ADC_GO bit in the start ADC measurement SFR (ADCGO, 0xD8). An interrupt is generated when the conversion is done and when the external voltage measurement is available in the VDCIN ADC value SFR (VDCINADC, 0xEF).
2.
Background External Voltage Measurements
Background external voltage measurements are disabled by default. To configure the background external voltage measurement mode, set an external voltage measurement interval in the peripheral ADC strobe period SFR (STRBPER, 0xF9). External voltage measurements are performed periodically in the background (see Table 49). When an external voltage conversion is complete, the new external voltage ADC value is compared to the last external voltage ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting in the VDCIN_DIFF[2:0] bits in the temperature and supply delta SFR (DIFFPROG, 0xF3), a VDCIN ADC flag is set. This VDCIN ADC flag is FVADC in the power management interrupt flag SFR (IPSMF, 0xF8), which is used for power supply management. This VDCIN ADC flag can be enabled to generate a PSM interrupt by setting the EVADC bit in the power management interrupt enable SFR (IPSME, 0xEC). This method allows external voltage measurements to take place completely in the background, only requiring MCU activity if the external voltage has changed more than a configurable delta. To set up background external voltage measurements, follow these steps: 1. Initiate a single external voltage measurement by setting the VDCIN_ADC_GO bit in the start ADC measurement SFR (ADCGO, 0xD8). Upon completion of this measurement, configure the VDCIN_DIFF[2:0] bits to establish the change in voltage that sets the FVDCIN in the power management interrupt flag SFR (IPSMF, 0xF8). Set up the interval for background external voltage measurements by configuring the VDCIN_PERIOD[1:0] bits in the peripheral ADC strobe period SFR (STRBPER, 0xF9).
Battery ADC in PSM0, PSM1, and PSM2
Depending on the operating mode, a battery conversion is initiated only by certain actions. * In PSM0 operating mode, the 8052 is active. Battery measurements are available in the background measurement mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is battery powered. Single battery measurements can be initiated by setting the BATT_ADC_GO bit in the start ADC measurement SFR (ADCGO, 0xD8). Background battery measurements are not available. In PSM2 operating mode, the 8052 is not active. Unlike temperature and VDCIN measurements, the battery conversions are not available in this mode.
*
*
Battery ADC Interrupt
The battery ADC can generate an ADC interrupt when at least one of the following conditions occurs: * The new battery ADC value is smaller than the value set in the battery detection threshold SFR (BATVTH, 0xFA), indicating a battery voltage loss. A single battery measurement initiated by setting the BATT_ADC_GO bit finishes.
*
When the battery flag (FBAT) is set in the power management interrupt flag SFR (IPSMF, 0xF8), a new ADC value is available in the battery ADC value SFR (BATADC, 0xDF). This battery flag can be enabled as a source of the PSM interrupt to generate a PSM interrupt every time the battery drops below a set voltage threshold or after a single conversion initiated by setting the BATT_ADC_GO bit is ready. The battery ADC value SFR (BATADC, 0xDF) is updated with a new value only when the battery flag is set in the power management interrupt flag SFR (IPSMF, 0xF8).
2.
3.
EXTERNAL VOLTAGE MEASUREMENT
The ADE5166/ADE5169/ADE5566/ADE5569 include a dedicated ADC to provide a digital measurement of an external voltage on the VDCIN pin. An 8-bit SFR, the VDCIN ADC value SFR (VDCINADC, 0xEF), holds the results of the conversion. The resolution of the external voltage measurement is 15.3 mV/LSB. There are two ways to initiate an external voltage conversion: a single external voltage measurement or background external voltage measurements.
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ADE5166/ADE5169/ADE5566/ADE5569
External Voltage ADC in PSM1 and PSM2
An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE5166/ADE5169/ ADE5566/ADE5569. * In PSM0 operating mode, the 8052 is active. External voltage measurements are available in the background measurement mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is powered from battery. Single external voltage measurements can be initiated by setting the VDCIN_ADC_GO bit in the start ADC measurement SFR (ADCGO, 0xD8). Background external voltage measurements are not available. In PSM2 operating mode, the 8052 is not active. External voltage conversions are available through the background measurement mode only.
Preliminary Technical Data
External Voltage ADC Interrupt
The external voltage ADC can generate an ADC interrupt when at least one of the following conditions occurs: * The difference between the new external voltage ADC value and the last external voltage ADC value generating an ADC interrupt is larger than the value set in the VDCIN_DIFF[2:0] bits in the temperature and supply delta SFR (DIFFPROG, 0xF3). The external voltage ADC conversion initiated by setting VDCIN_ADC_GO finishes.
*
*
*
When the ADC interrupt occurs, a new value is available in the VDCIN ADC value SFR (VDCINADC, 0xEF). Note that there is no flag associated with this interrupt.
The external voltage ADC in the VDCIN ADC value SFR (VDCINADC, 0xEF) is updated with a new value only when an external voltage ADC interrupt occurs.
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Preliminary Technical Data 8052 MCU CORE ARCHITECTURE
The ADE5166/ADE5169/ADE5566/ADE5569 has an 8052 MCU core and uses the 8051 instruction set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and enhancements that have been made to it in the ADE5166/ADE5169/ADE5566/ ADE5569. The special function register (SFR) space is mapped into the upper 128 bytes of internal data memory space and is accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADE5166/ADE5169/ADE5566/ ADE5569 via the SFR area is shown in Figure 59. All registers except the program counter (PC), instruction register (IR) and the four general-purpose register banks reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals.
ADE5166/ADE5169/ADE5566/ADE5569
62kB ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE PROGRAM/DATA MEMORY 256 BYTES GENERALPURPOSE RAM
ENERGY MEASUREMENT POWER MANAGEMENT RTC
8051-COMPATIBLE CORE PC IR
REGISTER BANKS
128-BYTE SPECIAL FUNCTION REGISTER AREA
LCD DRIVER TEMPERATURE ADC BATTERY ADC
2kB XRAM
Figure 59: ADE5166/ADE5169/ADE5566/ADE5569 Block Diagram
MCU REGISTERS
The registers used by the MCU are summarized hereafter.
Table 56. 8051 SFRs
SFR A B PSW PCON DPL DPH DPTR SP SPH STCON CFG Address 0xE0 0xF0 0xD0 0x87 0x82 0x83 0x82 and 0x83 0x81 0xB7 0xBF 0xAF Bit Addressable Yes Yes Yes No No No No No No No No Description Accumulator Auxiliary Math Program Status Word (see Table 57) Power Control (see Table 58) Data Pointer Low (see Table 59) Data Pointer High (see Table 60) Data Pointer (see Table 61) Stack Pointer (see Table 62) Stack Pointer High (see Table 63) Stack Boundary (see Table 64) Configuration (see Table 65)
Table 57. Program Status Word SFR (PSW, 0xD0)
Bit 7 6 5 4, 3 Address 0xD7 0xD6 0xD5 0xD4, 0xD3 Mnemonic CY AC F0 RS1, RS0 Description Carry Flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. Auxiliary Carry Flag. Modified by ADD, and ADDC instructions. General-Purpose Flag Available to the User. Register Bank Select Bits. RS1 RS0 Selected Bank 0 0 0 0 1 1 1 0 2 1 1 3 Overflow Flag. Modified by ADD, ADDC, SUBB, MUL and DIV instructions. General-Purpose Flag Available to the User. Parity Bit. The number of bits set in the accumulator added to the value of the parity bit is always an even number.
2 1 0
0xD2 0xD1 0xD0
OV F1 P
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OTHER ON-CHIP PERIPHERALS: SERIAL I/O WDT TIMERS
ADE5166/ADE5169/ADE5566/ADE5569
Table 58. Program Control SFR (PCON, 0x87)
Bit 7 6 to 0 Mnemonic SMOD Reserved Default 0 0 Description Double baud rate control. Reserved, should be left cleared.
Preliminary Technical Data
Table 59. Data Pointer Low SFR (DPL, 0x82)
Bit 7 to 0 Mnemonic DPH[7:0] Default 0 Description Contain the low byte of the data pointer.
Table 60. Data Pointer High SFR (DPH, 0x83)
Bit 7 to 0 Mnemonic DPH[7:0] Default 0 Description Contain the high byte of the data pointer.
Table 61. Data Pointer SFR (DPTR, 0x82 and 0x83)
Bit 15 to 0 Mnemonic DP[15:0] Default 0 Description Contain the 2-byte address of the data pointer. DPTR is a combination of DPH and DPL SFRs.
Table 62. Stack Pointer SFR (SP, 0x81)
Bit 7 to 0 Mnemonic SP[7:0] Default 0 Description Contain the eight LSBs of the pointer for the stack.
Table 63. Stack Pointer High SFR (SPH, 0xB7)
Bits 7 6 5 4 3 2 1 0 Mnemonic Reserved SBFLG SSA[10] SSA[9] SSA[8] SP[10] SP[9] SP[8] Default 1 0 0 0 1 0 0 1 Description Reserved. Stack bottom flag. Stack Starting Address Bit 10. Stack Starting Address Bit 9. Stack Starting Address Bit 8. Stack Address Bit 10. Stack Address Bit 9. Stack Address Bit 8.
Table 64. Stack Boundary SFR (STCON, 0xBF)
Bits 7 to 3 2 Mnemonic WTRLINE INT_RST Default 0 0 Description Contains the stack water line setting bits. Interrupt/reset selection bit. 0 An interrupt is issued when a stack violation occurs. 1 A reset is issued when a stack violation occurs. Stack boundary enable bit. Waterline flag.
1 0
SBE WTRLFG
0 0
Table 65. Configuration SFR (CFG, 0xAF)
Bit 7 6 Mnemonic Reserved EXTEN Default 1 0 Description This bit should be left set for proper operation. Enhanced UART enable bit. EXTEN Result 0 Standard 8052 UART without enhanced error checking features 1 Enhanced UART with enhanced error checking--see the UART Additional Features section. Synchronous communication selection bit. SCPS Result 0 I2C port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs. 1 SPI port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs
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5
SCPS
0
Preliminary Technical Data
Bit 4 Mnemonic MOD38EN Default 0
ADE5166/ADE5169/ADE5566/ADE5569
Description 38 kHz Modulation Enable Bit MOD38EN Result 0 38kHz modulation is disabled. 1 38kHz modulation is enabled on the pins selected by the MOD38[7:0] bits in the EPCFG SFR. Reserved. Should be left cleared. XREN[1:0] Result Enable MOVX instruction to use 256 bytes of Extended RAM. XREN1 OR XREN0 = 1 XREN1 AND Disable MOVX instruction. XREN0 = 0
3 to 2 1 to 0
Reserved XREN1, XREN0
00 01
BASIC 8052 REGISTERS
Program Counter (PC)
The program counter holds the 2-byte address of the next instruction to be fetched. The PC is initialized with 0x00 at reset and is incremented after each instruction is performed. Note that the amount that is added to the PC depends on the number of bytes in the instruction, so the increment can range from one to three bytes. The program counter is not directly accessible to the user but can be directly modified by CALL and JMP instructions that change which part of the program is active.
B Register
The B register is used by the multiply and divide instructions, MUL AB and DIV AB, to hold one of the operands. Because it is not used for many instructions, it can be used as a scratchpad register like those in the register banks. The B register is stored in the SFR space (see Table 56).
Program Status Word (PSW)
The PSW register reflects the status of arithmetic and logical operations through carry, auxiliary carry and overflow flags. The parity flag reflects the parity of the contents of the accumulator, which can be helpful for communication protocols. The PSW bits are described in Table 57. The program status word SFR (PSW, 0xD0) is bit addressable.
Instruction Register (IR)
The instruction register holds the opcode of the instruction being executed. The opcode is the binary code that results from assembling an instruction. This register is not directly accessible to the user.
Data Pointer (DPTR)
The data pointer is made up of two 8-bit registers: DPH (high byte), and DPL (low byte). These provide memory addresses for internal code and data access. The DPTR can be manipulated as a 16-bit register (DPTR = DPH, DPL), or as two independent 8-bit registers (DPH, DPL)--see Table 59 and Table 60. The 8052 MCU core architecture supports dual data pointers (see the 8052 MCU Core Architecture section).
Register Banks
There are four banks containing 8-byte-wide registers each, for a total of 32 bytes of registers. These registers are convenient for temporary storage of mathematical operands. An instruction involving the accumulator and a register can be executed in one clock cycle as opposed to 2 clock cycles to perform an instruction involving the accumulator and a literal or a byte of general purpose RAM. The register banks are located in the first 32 bytes of RAM. The active register bank is selected by the RS0 and RS1 bits in the program status word SFR (PSW, 0xD0).
Stack Pointer (SP)
The stack pointer keeps track of the current address of the top of the stack. To push a byte of data onto the stack, the stack pointer is incremented and the data is moved to the new top of the stack. To pop a byte of data off the stack, the top byte of data is moved into the awaiting address and the stack pointer is decremented. The stack is a last in first out (LIFO) method of data storage because the most recent addition to the stack is the first to come off it. The stack is utilized during CALL and RET instructions to keep track of the address to move into the PC when returning from the function call. The stack is also manipulated when vectoring for interrupts, to keep track of the prior state of the PC. The stack resides in the upper part of the extended internal RAM. The SP[7:0] and SPH[2:0] registers hold the address of the stack in the extended RAM. The advantage of this solution
Accumulator
The accumulator is a working register, storing the results of many arithmetic or logical operations. The accumulator is used in more than half of the 8052 instructions where it is usually referred to as A. The status register (PSW) constantly monitors the number of bits that are set in the accumulator to determine if it has even or odd parity. The accumulator is stored in the SFR space (see Table 56).
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is that the use of the general-purpose RAM can be limited to data storage. The use of the extended internal RAM can be limited to the stack, or alternatively split between the stack and data storage if more space is required. This separation limits the chance of data corruption because the stack can be contained in the upper section of the XRAM and does not overflow into the lower section containing data. Data can still be stored in extended RAM by using the MOVX command. The default starting address for the stack is 0x100, electing the upper 1792 bytes of XRAM for the stack operation. The starting address can be reconfigured to reduce the stack by writing to Bits SPH[5:3]. These three bits set the value of the three most significant bits of the stack pointer. For example, setting the SPH[5:3] to a value of 110b moves the default starting address of the stack to 0x600, allowing the highest 512 bytes of the XRAM to be used for stack operation. If the situation occurs that the stack reaches the top of the XRAM and overflows, the stack pointer rolls over to the default starting address that is written in SPH[5:3]. Care should be taken if altering the default starting address of the stack because unwanted overwrite operations may occur should the stack overflow or underflow.
Preliminary Technical Data
when STCON[2] is high, a reset also occurs. If an interrupt response is selected, the watchdog interrupt service routine is entered assuming that there is no higher level interrupt currently being serviced. It should be noted that once STCON[1] is enabled, an interrupt(or reset) triggers if the stack boundary is violated, regardless of the status of the EA bit in the IE register. This is because the watchdog interrupt is automatically configured as a high priority interrupt and, therefore, is not disabled by clearing EA. When STCON[1] is low, the feature is completely disabled and no pending interrupts are generated. There are two separate flags associated with the stack boundary protection, allowing the cause of the violation to be determined. When the waterline is exceeded, a flag is set in Bit 0 of the stack boundary SFR (STCON, 0xBF) indicating that the reset/interrupt was initiated by the stack waterline monitor. This flag remains high until the stack pointer falls below the waterline and the user clears the flag in software. A waterline or watchdog reset alone does not clear the flag. To successfully clear the flag, the software clear must occur while the stack pointer is below the waterline. Note that the stack pointer should never be altered while in the interrupt service routine because this leads to the program returning to a different section of the program and therefore malfunctioning. An external reset also causes the waterline flag to reset. When an attempt has been made to move the stack pointer below the stack starting address, a flag is set in the stack pointer high SFR (SPH, 0xB7), indicating that the reset/interrupt was initiated by the stack bottom monitor. Once again, a boundary or watchdog reset alone does not clear this flag, and the user must clear the flag in software to successfully acknowledge the event. Note that if SPH[5:3] and SPH[2:0] are altered simultaneously to reduce the default stack starting address, when the stack boundary condition is enabled, a stack violation condition occurs and the stack bottom flag, SPH[6], is initiated. To avoid this condition, it is recommended that the default stack starting address remain at 0x100 or be increased further up the XRAM. A useful implementation of the waterline feature is to determine the amount of space required for the stack and allow a suitable default starting address to be selected. This optimizes the use of the additional XRAM space, allowing it to be used for data storage. To obtain this information, the waterline should be set to the estimated stack maximum and the interrupt enabled. If the stack exceeds the estimated maximum, the interrupt triggers, and the waterline level should be increased in the interrupt service routine. Before returning to the main program, the waterline interrupt status flag should be cleared. This program continues to jump to the waterline service routine until the stack no longer exceeds the waterline level and the maximum stack level has been determined. The stack boundary feature can be protected by clearing the second most significant bit in Flash Location 0xF7FF (see the Protecting the Flash section). If this protection bit is enabled,
Stack Boundary Protection As a warning signal that the stack pointer is extending outside the specified range, a stack boundary protection feature is included. This feature is controlled through the stack boundary SFR (STCON, 0xBF) and is disabled by default. To enable this feature, the boundary protection enable bit should be set in the STCON SFR.
The stack boundary protection works in two ways to protect the remainder of the XRAM from being corrupted. The waterline detection feature monitors the top of the stack and warns the user when the stack pointer is reaching the overflow point. By setting STCON[7:3], the level of the water line below the top of the XRAM can be set. For example, by setting STCON[7:3] to the maximum value of 0x1F, the waterline is set to its minimum value of 0x7FF - 0x1F = 0x7F0. Similarly, by setting STCON[7:3] to 0x1, the waterline is set at the top of the RAM space, 0x7FE. Note that if STCON[7:3] is set to 000b, then the feature is effectively disabled and no interrupt or reset is generated. The bottom of the stack is also preserved by the stack boundary feature. Should the stack pointer be written to a value lower than the default stack starting address defined in the SPH[5:3], a warning is issued and the perpetrating command is ignored. The protection for both the waterline and the stack starting address are enabled simultaneously by setting Bit 1 in the STCON SFR. When enabled, the stack boundary protection can be configured to either reset the part or trigger an interrupt when a stack violation occurs. The value of STCON[2] determines the response of the part. When STCON[2] is set to 0x1 and the stack pointer exceeds the waterline, the part resets immediately no matter what other routines are in progress. If an attempt is made to move the stack pointer below the default stack starting address
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Preliminary Technical Data
the stack boundary protection is enabled and fixed to issue an interrupt should an event occur. STCON[1] and STCON[2] can therefore not be altered when the protection bit is set. Once the protection bit is set, the default stack starting address, SPH[5:3], can only be written once before becoming fixed. It is therefore recommended that this feature be configured for the application before the stack boundary protection bit is written in the flash.
0x7FF 0x7FF-STCON[7:3] WATERLINE
ADE5166/ADE5169/ADE5566/ADE5569
unlike standard 8052 products, provide internal nonvolatile Flash memory so that an external code space is unnecessary. The on-chip LCD driver requires many pins, some of which are dedicated for LCD functionality and others that can be configured at LCD or general-purpose I/O. Due to the limited number of I/O pins, the ADE5166/ADE5169/ADE5566/ADE5569 do not allow access to external code and data spaces. The ADE5166/ADE5169/ADE5566/ADE5569 provide 20 pins that can be used for general purpose I/O. These pins are mapped to Port 0, Port 1, and Port 2, and are accessed through three bit-addressable 8052 SFRs: P0, P1, and P2. Another enhanced feature of the ADE5166/ADE5169/ADE5566/ADE5569 is that the weak pull-ups standard on 8052 Port 1, Port 2, and Port 3 can be disabled to make open-drain outputs, as is standard on Port 0. The weak pull-ups can be enabled on a pin-by-pin basis (see the I/O Ports section).
07411-119
{SPH[5:3], 0x00}
STACK STARTING ADDRESS
2kB OF ON-CHIP x-RAM 0xFF 256 BYTES OF RAM (DATA) 0x00 0x00
Power Control Register (PCON, 0x87)
The 8052 core defines two power-down modes; power-down and idle. The ADE5166/ADE5169/ADE5566/ADE5569 enhance the power control capability of the traditional 8052 MCU with additional power management functions. The POWCON register is used to define power control specific functionality for the ADE5166/ADE5169/ADE5566/ADE5569. The program control SFR (PCON, 0x87) is not bit addressable (see Power Management section). The ADE5166/ADE5169/ADE5566/ADE5569 provide many other peripherals not standard to the 8052 core. * * * * * * * * * * ADE energy measurement DSP Full RTC LCD driver Battery switchover/power management Temperature ADC Battery ADC SPI/I2C communication Flash memory controller Watchdog timer Secondary UART port
Figure 60. Extended Stack Pointer Operation
STANDARD 8052 SFRS
The standard 8052 special function registers include the accumulator, B, PSW, DPTR, and SP SFRs described in the Basic 8052 Registers section. The 8052 also defines standard timers, serial port interfaces, interrupts, I/O ports and power down modes.
Timer SFRs
The 8052 contains three 16-bit timers, the identical Timer0 and Timer1, as well as a Timer2. These timers can also function as event counters. Timer2 has a capture feature where the value of the timer can be captured in two 8-bit registers upon the assertion of an external input signal (see the Timers section).
Serial Port SFRs
The two full-duplex serial port peripherals each require two registers, one for setting up the baud rate and other communication parameters, and another byte for the transmit/receive buffer. TheADE5166/ADE5169/ADE5566/ADE5569 also provide enhanced serial port functionality with a dedicated timer for baud rate generation with a fractional divisor and additional error detection. See the UART Serial Interface section and the UART2 Serial Interface section for details.
MEMORY OVERVIEW
The ADE5166/ADE5169/ADE5566/ADE5569 contain three memory blocks. * * * 62 kB of on-chip Flash/EE program and data memory 256 bytes of general-purpose RAM 2 kB of internal extended RAM (XRAM)
Interrupt SFR
There is a two-tiered interrupt system standard in the 8052 core. The priority level for each interrupt source is individually selectable as high or low. The TheADE5166/ADE5169/ADE5566/ ADE5569 enhance this interrupt system by creating in essence a third interrupt tier for a highest priority power supply management interrupt, PSM (see the Interrupt System section).
I/O Port SFRs
The 8052 core supports four I/O ports, P0 through P3, where Port 0 and Port 2 are typically used for access to external code and data spaces. The ADE5166/ADE5169/ADE5566/ADE5569,
The 256 bytes of general-purpose RAM shares the upper 128 bytes of its address space with special function registers. All of the memory spaces are shown in Figure 59. The addressing mode specifies which memory space to access.
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ADE5166/ADE5169/ADE5566/ADE5569
General-Purpose RAM
General-purpose RAM resides in Memory Location 0x00 through Memory Location 0xFF. It contains the register banks.
0x7F
Preliminary Technical Data
BYTE ADDRESS 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 BIT ADDRESSES (HEXA) 7E 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
07411-060
GENERAL-PURPOSE AREA
0x30 0x2F
BANKS SELECTED VIA BITS IN PSW 11
BIT-ADDRESSABLE (BIT ADDRESSES)
0x20 0x1F 0x18 0x17
0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20
10
0x10 0x0F
FOUR BANKS OF EIGHT REGISTERS R0 TO R7
Figure 63. Bit Addressable Area of General-Purpose RAM
01
0x08 0x07
07411-058
00
RESET VALUE OF STACK POINTER
0x00
Bit addressing can be used for instructions that involve Boolean variable manipulation and program branching (see the Instruction Set section).
Figure 61. Lower 128 Bytes of Internal Data Memory
Special Function Registers
Special function registers are registers that affect the function of the 8051 core or its peripherals. These registers are located in RAM with Address 0x80 through Address 0xFF. They are only accessible through direct addressing, as shown in Figure 62. The individual bits of some of the SFRs can be accessed for use in Boolean and program branching instructions. These SFRs are labeled as bit addressable and the bit addresses are given in Table 14.
Address 0x80 through Address 0xFF of general-purpose RAM are shared with the special function registers. The mode of addressing determines which memory space is accessed, as shown in Figure 62.
0xFF ACCESSIBLE BY INDIRECT ADDRESSING ONLY ACCESSIBLE BY DIRECT AND INDIRECT ADDRESSING ACCESSIBLE BY DIRECT ADDRESSING ONLY
0x80 0x7F
0x00
07411-059
Extended Internal RAM (XRAM)
GENERAL-PURPOSE RAM SPECIAL FUNCTION REGISTERS (SFRs)
Figure 62. General-Purpose RAM and SFR Memory Address Overlap
The 8052 core also has the means to access individual bits of certain addresses in the general-purpose RAM and special function memory spaces. The individual bits of general-purpose RAM, Address 0x20 to Address 0x2F, can be accessed through Bit Address 0x00 to Bit Address 0x7F. The benefit of bit addressing is that the individual bits can be accessed quickly, without the need for bit masking, which takes more code memory and execution time. The bit addresses for general-purpose RAM Address 0x20 through Address 0x2F can be seen in Figure 63.
0x00
Figure 64: Extended Internal RAM (XRAM) Space
Code Memory
Code and data memory are stored in the 62 kB flash memory space. No external code memory is supported. To access code memory, code indirect addressing is used.
ADDRESSING MODES
The 8052 core provides several addressing modes. The addressing mode determines how the core interprets the memory location or data value specified in assembly language code. There are six addressing modes, as shown in Table 66.
Rev. PrB | Page 78 of 148
07411-061
Both direct and indirect addressing can be used to access generalpurpose RAM from 0x00 through 0x7F, but indirect addressing must be used to access general-purpose RAM with addresses in the range from 0x80 through 0xFF because they share the same address space with the special function registers (SFRs).
The ADE5166/ADE5169/ADE5566/ADE5569 provide 2 kB of extended on-chip RAM. No external RAM is supported. This RAM is located in Address 0x00 through Address 0x7FF in the extended RAM space. To select the extended RAM memory space, the extended indirect addressing modes are used.
0x7FF 2kB OF EXTENDED INTERNAL RAM (XRAM)
Preliminary Technical Data
Table 66. 8052 Addressing Modes
Addressing Mode Immediate Direct Example MOV A, #A8h MOV DPTR, #A8h MOV A, A8h MOV A, IE MOV A, R0 MOV A, @R0 MOVX A, @DPTR MOVX A, @R0 MOVC A, @A+DPTR MOVC A, @A+PC JMP @A+DPTR Bytes 2 3 2 2 1 1 1 1 1 1 1 Core Clock Cycles 2 3 2 2 1 2 4 4 4 4 3
ADE5166/ADE5169/ADE5566/ADE5569
ADE5566/ADE5569 provide 2 kB of internal extended RAM (XRAM), accessed through MOVX instructions. External memory spaces are not supported on the ADE5166/ADE5169/ ADE5566/ADE5569. In extended direct addressing mode, the DPTR register points to the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x100 to the accumulator:
MOV MOVX DPTR,#100h A,@DPTR
Indirect Extended Direct Extended Indirect Code Indirect
These two instructions require a total of seven clock cycles and four bytes of storage in the program memory.
Extended Indirect Addressing
The internal extended RAM is accessed through a pointer to the address in indirect addressing mode. The ADE5166/ADE5169/ ADE5566/ADE5569 provide 2 kB of internal extended RAM, accessed through MOVX instructions. External memory is not supported on the ADE5166/ADE5169/ADE5566/ADE5569. In extended indirect addressing mode, a register holds the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x80 to the accumulator: MOV R0,#80h MOVX A,@R0 These two instructions require six clock cycles and three bytes of storage. Note that there are 2 kB of extended RAM, so both extended direct and extended indirect addressing can cover the whole address range. There is a storage and speed advantage to using extended indirect addressing because the additional byte of addressing available through the DPTR register that is not needed is not stored. From the three examples demonstrating the access of internal RAM from 0x80 through 0xFF and extended internal RAM from 0x00 through 0xFF, it can be seen that it is most efficient to use the entire internal RAM accessible through indirect access before moving to extended RAM.
Immediate Addressing
In immediate addressing, the expression entered after the number sign (#) is evaluated by the assembler and stored in the memory address specified. This number is referred to as a literal because it refers only to a value and not to a memory location. Instructions using this addressing mode is slower than those between two registers because the literal must be stored and fetched from memory. The expression can be entered as a symbolic variable or an arithmetic expression; the value is computed by the assembler.
Direct Addressing
With direct addressing, the value at the source address is moved to the destination address. Direct addressing provides the fastest execution time of all the addressing modes when an instruction is performed between registers using direct addressing. Note that indirect or direct addressing modes can be used to access general-purpose RAM Address 0x00 through Address 0x7F. An instruction with direct addressing that uses an address between 0x80 and 0xFF is referring to a special function memory location.
Indirect Addressing
With indirect addressing, the value pointed to by the register is moved to the destination address. For example, to move the contents of internal RAM Address 0x82 to the accumulator, use the following two instructions, which require a total of four clock cycles and three bytes of storage in the program memory:
MOV MOV R0,#82h A,@R0
Code Indirect Addressing
The internal code memory can be accessed indirectly. This can be useful for implementing lookup tables and other arrays of constants that are stored in Flash. For example, to move the data stored in Flash memory at Address 0x8002 into the accumulator:
MOV CLR MOVX DPTR,#8002h A A,@A+DPTR
Indirect addressing allows addresses to be computed, and is useful for indexing into data arrays stored in RAM. Note that an instruction that refers to Addresses 0x00 through Address 0x7F is referring to internal RAM, and indirect or direct addressing modes can be used. An instruction with indirect addressing that uses an address between 0x80 and 0xFF is referring to internal RAM, not to an SFR.
Extended Direct Addressing
The DPTR register is used to access internal extended RAM in extended indirect addressing mode. The ADE5166/ADE5169/
The accumulator can be used as a variable index into the array of flash memory located at DPTR.
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ADE5166/ADE5169/ADE5566/ADE5569
INSTRUCTION SET
Preliminary Technical Data
Table 67 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 4-MIPS peak performance.
Table 67. Instruction Set
Mnemonic Arithmetic ADD A, Rn ADD A, @Ri ADD A, dir ADD A, #data ADDC A, Rn 1 1 ADDC A, @Ri ADDC A, dir ADDC A, #data SUBB A, Rn SUBB A, @Ri SUBB A, dir SUBB A, #data INC A INC Rn INC @ INC dir INC DPTR DEC A DEC Rn DEC @Ri DEC dir MUL AB DIV AB DA A Logic ANL A, Rn ANL A, @Ri ANL A, dir ANL A, #data ANL dir, A ANL dir, #data ORL A, Rn ORL A, @Ri ORL A, dir ORL A, #data ORL dir, A ORL dir, #data XRL A, Rn XRL A, @Ri XRL A, #data XRL dir, A XRL A, dir XRL dir, #data CLR A CPL A SWAP A RL A Description Add register to A Add indirect memory to A Add direct byte to A Add Immediate to A Add register to A with carry Add indirect memory to A with carry Add direct byte to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract indirect memory from A with borrow Subtract direct from A with borrow Subtract immediate from A with borrow Increment A Increment register Ri increment indirect memory Increment direct byte Increment data pointer Decrement A Decrement register Decrement indirect memory Decrement direct byte Multiply A by B Divide A by B Decimal Adjust A AND register to A AND indirect memory to A AND direct byte to A AND immediate to A AND A to direct byte AND immediate data to direct byte OR register to A OR indirect memory to A OR direct byte to A OR immediate to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR indirect memory to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR indirect memory to A Exclusive-OR immediate data to direct Clear A Complement A Swap nibbles of A Rotate A left
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Bytes 1 1 2 2 1 1 2 2 1 1 2 2 1 1 1 2 1 1 1 1 2 1 1 1 1 1 2 2 2 3 1 1 2 2 2 3 1 2 2 2 2 3 1 1 1 1
Cycles 1 2 2 2 1 2 2 2 1 2 2 2 1 1 2 2 3 1 1 2 2 9 9 2 1 2 2 2 2 3 1 2 2 2 2 3 1 2 2 2 2 3 1 1 1 1
Preliminary Technical Data
Mnemonic RLC A RR A RRC A Data Transfer MOV A, Rn MOV A, @Ri MOV Rn, A MOV @Ri, A MOV A, dir MOV A, #data MOV Rn, #data MOV dir, A MOV Rn, dir MOV dir, Rn MOV @Ri, #data MOV dir, @Ri MOV @Ri, dir MOV dir, dir MOV dir, #data MOV DPTR, #data MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH dir POP dir XCH A, Rn XCH A, @Ri XCHD A, @Ri XCH A, dir Boolean CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C, /bit ORL C, bit ORL C, /bit OR MOV C, bit MOV bit, C Branching JMP @A+DPTR RET RETI ACALL addr11 AJMP addr11 SJMP rel JC rel Description Rotate A left Through carry Rotate A right Rotate A right through carry Move register to A Move indirect memory to A Move A to register Move A to indirect memory Move direct byte to A Move immediate to A Move register to immediate Move A to direct byte Move register to direct byte Move direct to register Move immediate to indirect memory Move indirect to direct memory Move direct to indirect memory Move direct byte to direct byte Move immediate to direct byte Move immediate to data pointer Move code byte relative DPTR to A Move code byte relative PC to A Move external (A8) data to A Move external (A16) data to A Move A to external data (A8) Move A to external data (A16) Push direct byte onto stack Pop direct byte from stack Exchange A and register Exchange A and indirect memory Exchange A and indirect memory nibble Exchange A and direct byte Clear carry Clear direct bit Set carry Set direct bit Complement carry Complement direct bit AND direct bit and carry AND direct bit inverse to carry OR direct bit and carry Direct bit inverse to carry Move direct bit to carry Move carry to direct bit Jump indirect relative to DPTR Return from subroutine Return from interrupt Absolute jump to subroutine Absolute jump unconditional Short jump (relative address) Jump on carry equal to 1
ADE5166/ADE5169/ADE5566/ADE5569
Bytes 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 3 3 1 1 1 1 1 1 2 2 1 1 1 2 1 2 1 2 1 2 2 2 2 2 2 2 1 1 1 2 2 2 2 Cycles 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 2 3 3 3 4 4 4 4 4 4 2 2 1 2 2 2 1 2 1 2 1 2 2 2 2 2 2 2 3 4 4 3 3 3 3
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ADE5166/ADE5169/ADE5566/ADE5569
Mnemonic JNC rel JZ rel JNZ rel DJNZ Rn, rel LJMP LCALL addr16 JB bit, rel JNB bit, rel JBC bit, rel CJNE A, dir, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ dir, rel Miscellaneous NOP Description Jump on carry = 0 Jump on accumulator = 0 Jump on accumulator 0 Decrement register, JNZ relative Long jump unconditional Long jump to subroutine Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Compare A, direct JNE relative Compare A, immediate JNE relative Compare register, immediate JNE relative Compare indirect, immediate JNE relative Decrement direct byte, JNZ relative No operation
Preliminary Technical Data
Bytes 2 2 2 2 3 3 3 3 3 3 3 3 3 3 1 Cycles 3 3 3 3 4 4 4 4 4 4 4 4 4 4 1
READ-MODIFY-WRITE INSTRUCTIONS
Some 8052 instructions read the latch and others read the pin. The state of the pin is read for instructions that input a port bit. Instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and rewrite it to the latch. Because these instructions involve modifying the port, it is assumed that the pins being modified are outputs, so the output state of the pin is read from the latch. This prevents a possible misinterpretation of the voltage level of a pin. For example, if a port pin is used to drive the base of a transistor, a 1 is written to the bit to turn on the transistor. If the CPU reads the same port bit at the pin rather than the latch, it reads the base voltage of the transistor and interprets it as Logic 0. Reading the latch rather than the pin returns the correct value of 1. The instructions that read the latch rather than the pins are called read-modify-write instructions and are listed in Table 68. When the destination operand is a port or a port bit, these instructions read the latch rather than the pin.
Table 68. Read-Modify-Write Instructions
Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV PX.Y,C1 CLR PX.Y1 SETB PX.Y1
1
INSTRUCTIONS THAT AFFECT FLAGS
Many instructions explicitly modify the carry bit, such as the MOV C bit and CLR C instructions. Other instructions that affect status flags are listed in this section.
ADD A, Source
This instruction adds the source to the accumulator. No status flags are referenced by the instruction.
Affected Status Flags
C Set if there is a carry out of Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. Set if there is a carry out of Bit 6 or a carry out of Bit 7, but not if both are set. Used to indicate an overflow for signed addition. This flag is set if two positive operands yield a negative result or if two negative operands yield a positive result. Set if there is a carry out of Bit 3. Cleared otherwise.
OV
AC
Example ANL P0, A ORL P1, A XRL P2, A JBC P1.1,LABEL CPL P2.0 INC P2 DEC P2 DJNZ P0, LABEL MOV P0.0, C CLR P0.0 SETB P0.0
Description Logic AND Logic OR Logic XOR Jump if Bit = 1 and clear bit Complement bit Increment Decrement Decrement and jump if not zero Move carry to Bit Y of Port X Clear Bit Y of Port X Set Bit Y of Port X
ADDC A, Source
This instruction adds the source and the carry bit to the accumulator. The carry status flag is referenced by the instruction.
Affected Status Flags
C Set if there is a carry out of Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. Set if there is a carry out of Bit 6 or a carry out of Bit 7, but not if both are set. Used to indicate an overflow for signed addition. This flag is set if two positive operands yield a negative result or if two negative operands yield a positive result. Set if there is a carry out of Bit 3. Cleared otherwise.
OV
These instructions read the port byte (all eight bits), modify the addressed bit, and write the new byte back to the latch.
AC
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Preliminary Technical Data
SUBB A, Source
This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag.
ADE5166/ADE5169/ADE5566/ADE5569
of Bit 0 to Bit 3 exceeds nine, 0x06 is added to the accumulator to correct the lower four bits. If the carry bit is set when the instruction begins, or if 0x06 is added to the accumulator in the first step, 0x60 is added to the accumulator to correct the higher four bits. The carry and AC status flags are referenced by this instruction.
Affected Status Flags
C Set if there is a borrow needed for Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned. Set if there is a borrow needed for Bit 6 or Bit 7, but not for both. Used to indicate an overflow for signed subtraction. This flag is set if a negative number subtracted from a positive yields a negative result or if a positive number subtracted from a negative number yields a positive result. Set if a borrow is needed for Bit 3. Cleared otherwise.
Affected Status Flag
C Set if the result is greater than 0x99. Cleared otherwise.
OV
RRC A
This instruction rotates the accumulator to the right through the carry flag. The old LSB of the accumulator becomes the new carry flag, and the old carry flag is loaded into the new MSB of the accumulator. The carry status flag is referenced by this instruction.
AC
Affected Status Flag
C Equal to the state of ACC[0] before execution of the instruction.
MUL AB
This instruction multiplies the accumulator by the B register. This operation is unsigned. The lower byte of the 16-bit product is stored in the accumulator and the higher byte is left in the B register. No status flags are referenced by the instruction.
RLC A
This instruction rotates the accumulator to the left through the carry flag. The old MSB of the accumulator becomes the new carry flag, and the old carry flag is loaded into the new LSB of the accumulator. The carry status flag is referenced by this instruction.
Affected Status Flags
C OV Cleared Set if the result is greater than 255. Cleared otherwise.
DIV AB
This instruction divides the accumulator by the B register. This operation is unsigned. The integer part of the quotient is stored in the accumulator and the remainder goes into the B register. No status flags are referenced by the instruction.
Affected Status Flag
C Equal to the state of ACC[7] before execution of the instruction.
CJNE Destination, Source, Relative Jump
This instruction compares the source value to the destination value and branches to the location set by the relative jump if they are not equal. If the values are equal, program execution continues with the instruction after the CJNE instruction. No status flags are referenced by this instruction.
Affected Status Flags
C OV Cleared Cleared unless the B register is equal to 0, in which case the results of the division are undefined and the OV flag is set.
Affected Status Flag
C Set if the source value is greater than the destination value. Cleared otherwise.
DA A
This instruction adjusts the accumulator to hold two 4-bit digits after the addition of two binary coded decimals (BCDs) with the ADD or ADDC instructions. If the AC bit is set or if the value
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ADE5166/ADE5169/ADE5566/ADE5569 DUAL DATA POINTERS
Each ADE5166/ADE5169/ADE5566/ADE5569 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON, 0xA7). DPCON features automatic hardware postincrement and postdecrement, as well as an automatic data pointer toggle. Note that this is the only section of the data sheet where the main and shadow data pointers are distinguished. Whenever the data pointer (DPTR) is mentioned elsewhere in the data sheet, active DPTR is implied. In addition, only the MOVC/MOVX @DPTR instructions automatically postincrement and postdecrement the DPTR. Other MOVC/MOVX instructions, such as MOVC PC or MOVC @Ri, do not cause the DPTR to automatically postincrement and postdecrement. To illustrate the operation of DPCON, the following code copies 256 bytes of code memory at Address 0xD000 into XRAM, starting from Address 0x0000:
Table 69. Data Pointer Control SFR (DPCON, 0xA7)
Bit 7 6 5, 4 Mnemonic DPT DP1m1, DP1m0 Default 0 0 0 MOV DPTR,#0
Preliminary Technical Data
;Main DPTR = 0 ;Select shadow DPTR
MOV DPCON,#55H
;DPTR1 increment mode ;DPTR0 increment mode ;DPTR auto toggling ON MOV DPTR,#0D000H MOVELOOP: CLR A MOVC A,@A+DPTR ;Post Inc DPTR ;Swap to Main DPTR(Data) MOVX @DPTR,A ;Increment main DPTR ;Swap Shadow DPTR(Code) MOV A, DPL JNZ MOVELOOP ;Put ACC in XRAM ;Get data ;DPTR = D000H
3, 2
DP0m1, DP0m0
0
1 0
DPSEL
0 0
Description Not implemented. Write don't care. Data pointer automatic toggle enable. Cleared by the user to disable autoswapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction. Shadow data pointer mode. These bits enable extra modes of the shadow data pointer operation, allowing more compact and more efficient code size and execution. DP1m1 DP1m0 Result (Behavior of the Shadow Data Pointer) 0 0 8052 behavior. 0 1 DPTR is postincremented after a MOVX or a MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction can be useful for moving 8-bit blocks to/from 16-bit devices. Main data pointer mode. These bits enable extra modes of the main data pointer operation, allowing more compact and more efficient code size and execution. DP0m1 DP0m0 Result (Behavior of the Main Data Pointer) 0 0 8052 behavior. 0 1 DPTR is postincremented after a MOVX or a MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction is useful for moving 8-bit blocks to/from 16-bit devices. Not implemented. Write don't care. Data pointer select. Cleared by the user to select the main data pointer, meaning that the contents of this 16-bit register are placed into the DPL SFR and DPH SFR. Set by the user to select the shadow data pointer, meaning that the contents of a separate 16-bit register appear in the DPL SRF and DPH SFR.
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Preliminary Technical Data INTERRUPT SYSTEM
The unique power management architecture of the ADE5166/ ADE5169/ADE5566/ADE5569 includes an operating mode (PSM2) where the 8052 MCU core is shut down. Events can be configured to wake the 8052 MCU core from the PSM2 operating mode. A distinction is drawn here between events that can trigger the wake-up of the 8052 MCU core and events that can trigger an interrupt when the MCU core is active. Events that can wake the core are referred to as wake-up events, whereas events that can interrupt the program flow when the MCU is active are called interrupts. See the 3.3 V Peripherals and Wake-Up Events section to learn more about events that can wake the 8052 core from PSM2. The ADE5166/ADE5169/ADE5566/ADE5569 provide 12 interrupt sources with three priority levels. The power management interrupt is at the highest priority level. The other two priority levels are configurable through the interrupt priority SFR (IP, 0xB8) and interrupt enable and Priority 2 SFR (IEIP2, 0xA9).
ADE5166/ADE5169/ADE5566/ADE5569
occur at the same time, the Priority 1 interrupt is serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level occur simultaneously, a polling sequence is observed (see the Interrupt Priority section).
INTERRUPT ARCHITECTURE
The ADE5166/ADE5169/ADE5566/ADE5569 possess advanced power supply management features. To ensure a fast response to time-critical power supply issues, such as a loss of line power, the power supply management interrupt should be able to interrupt any interrupt service routine. To enable the user to have full use of the standard 8052 interrupt priority levels, an additional priority level is added for the power supply management (PSM) interrupt. The PSM interrupt is the only interrupt at this highest interrupt priority level.
HIGH PSM PRIORITY 1 LOW PRIORITY 0
07411-063
STANDARD 8052 INTERRUPT ARCHITECTURE
The 8052 standard interrupt architecture includes two tiers of interrupts, where some interrupts are assigned a high priority and others are assigned a low priority.
HIGH PRIORITY 1
07411-062
Figure 66. Interrupt Architecture
See the Power Supply Management Interrupt (PSM) section for more information on the PSM interrupt.
LOW
PRIORITY 0
INTERRUPT REGISTERS
The control and configuration of the interrupt system is carried out through four interrupt-related SFRs, discussed in this section.
Figure 65. Standard 8052 Interrupt Priority Levels
A Priority 1 interrupt can interrupt the service routine of a Priority 0 interrupt, and if two interrupts of different priorities
Table 70. Interrupt SFRs
SFR IE IP IEIP2 WDCON Address 0xA8 0xB8 0xA9 0xC0 Default 0x00 0x00 0xA0 0x10 Bit Addressable Yes Yes No Yes
Description Interrupt enable (see Table 71). Interrupt priority (see Table 72). Interrupt enable and Priority 2 (see Table 73). Watchdog timer (see Table 78 and the Writing to the Watchdog Timer SFR (WDCON, 0xC0) section).
Table 71. Interrupt Enable SFR (IE, 0xA8)
Bit 7 6 5 4 3 2 1 0 Address 0xAF 0xAE 0xAD 0xAC 0xAB 0xAA 0xA9 0xA8 Mnemonic EA ETEMP ET2 ES ET1 EX1 ET0 EX0 Description Enables all interrupt sources. Set by the user. Cleared by the user to disable all interrupt sources. Enables the temperature ADC interrupt. Set by the user. Enables the Timer 2 interrupt. Set by the user. Enables the UART serial port interrupt. Set by the user. Enables the Timer 1 interrupt. Set by the user. Enables the External Interrupt 1 (INT1). Set by the user. Enables the Timer 0 interrupt. Set by the user. Enables External Interrupt 0 (INT0). Set by the user.
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ADE5166/ADE5169/ADE5566/ADE5569
Table 72. Interrupt Priority SFR (IP, 0xB8)
Bit 7 6 5 4 3 2 1 0 Address 0xBF 0xBE 0xBD 0xBC 0xBB 0xBA 0xB9 0xB8 Mnemonic PADE PTEMP PT2 PS PT1 PX1 PT0 PX0
Preliminary Technical Data
Description ADE energy measurement interrupt priority (1 = high, 0 = low). Temperature ADC interrupt priority (1 = high, 0 = low). Timer 2 interrupt priority (1 = high, 0 = low). UART serial port interrupt priority (1 = high, 0 = low). Timer 1 interrupt priority (1 = high, 0 = low). INT1 (External Interrupt 1) priority (1 = high, 0 = low). Timer 0 interrupt priority (1 = high, 0 = low). INT0 (External Interrupt 0) priority (1 = high, 0 = low).
Table 73. Interrupt Enable and Priority 2 SFR (IEIP2, 0xA9)
Bit 7 6 5 4 3 2 1 0 Mnemonic PS2 PTI ES2 PSI EADE ETI EPSM ESI Description UART2 serial port interrupt priority (1 = high, 0 = low). RTC interrupt priority (1 = high, 0 = low). Enables the UART2 serial port interrupt. Set by the user. SPI/I2C interrupt priority (1 = high, 0 = low). Enables the energy metering interrupt (ADE). Set by the user. Enables the RTC interval timer interrupt. Set by the user. Enables the PSM power supply management interrupt. Set by the user. Enables the SPI/I2C interrupt. Set by the user.
INTERRUPT PRIORITY
If two interrupts of the same priority level occur simultaneously, the polling sequence is observed (as shown in Table 74).
Table 74. Priority Within Interrupt Level
Source IPSM IRTC IADE WDT ITEMP IE0 TF0 IE1 TF1 ISPI/I2CI RI/TI TF2/EXF2 RI2/TI2 Priority 0 (Highest) 1 2 3 4 5 6 7 8 9 10 11 12 (Lowest) Description Power supply management interrupt. RTC interval timer interrupt. ADE energy measurement interrupt. Watchdog timer overflow interrupt. Temperature ADC interrupt. External Interrupt 0. Timer/Counter 0 interrupt. External Interrupt 1. Timer/Counter 1 interrupt. SPI/I2C interrupt. UART Serial Port interrupt. Timer/Counter 2 interrupt. UART2 serial port interrupt
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Preliminary Technical Data
INTERRUPT FLAGS
ADE5166/ADE5169/ADE5566/ADE5569
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 75 and Table 76, respectively. Most of the interrupts have flags associated with them.
Table 75. Interrupt Flags
Interrupt Source IE0 TF0 IE1 TF1 RI + TI RI2 + TI2 TF2 + EXF2 ITEMP (Temperature ADC) IPSM (Power Supply) IADE (Energy Measurement DSP) Flag TCON.1 TCON.5 TCON.3 TCON.7 SCON.1 SCON.0 SCON2.1 SCON2.0 T2CON.7 T2CON.6 N/A IPSMF.6 MIRQSTL.7 Bit Name IE0 TF0 IE1 TF1 TI RI TI2 RI2 TF2 EXF2 N/A FPSM ADEIRQFLAG Description External Interrupt 0. Timer 0. External Interrupt 1. Timer 1. Transmit interrupt. Receive interrupt. Transmit 2 interrupt Receive 2 interrupt Timer 2 overflow flag. Timer 2 external flag. Temperature ADC interrupt. Does not have an interrupt flag associated with it. PSM interrupt flag. Read MIRQSTH, MIRQSTM, MIRQSTL.
Table 76. Status Flags
Interrupt Source ITEMP (Temperature ADC) ISPI/I2CI IRTC (RTC Interval Timer) WDT (Watchdog Timer)
1
Flag N/A SPI2CSTAT1 SPI2CSTAT TIMECON.6 TIMECON.2 WDCON.2
Bit Address N/A N/A N/A ALFLAG ITFLAG WDS
Description Temperature ADC interrupt. Does not have a status flag associated with it. SPI interrupt status register. I2C interrupt status register. RTC alarm flag. RTC interrupt flag. Watchdog timeout flag.
There is no specific flag for ISPI/I2CI; however, all flags for SPI2CSTAT need to be read to assess the reason for the interrupt.
A functional block diagram of the interrupt system is shown in Figure 67. Note that the PSM interrupt is the only interrupt in the highest priority level. If an external wake-up event occurs to wake the ADE5166/ ADE5169/ADE5566/ADE5569 from PSM2, a pending external interrupt is generated. When the EX0 or EX1 bit in the interrupt enable SFR (IE, 0xA8) is set to enable external interrupts, the program counter is loaded with the IE0 or IE1 interrupt vector. The IE0 and IE1 interrupt flags in the TCON register are not affected by events that occur when the 8052 MCU core is shut down during PSM2 (see the Power Supply Management Interrupt (PSM) section). The temperature ADC and I2C/SPI interrupts are latched such that pending interrupts cannot be cleared without entering their respective interrupt service routines. Clearing the I2C/SPI status bits in the SPI interrupt status SFR (SPISTAT, 0xEA) does not cancel a pending I2C/SPI interrupt. These interrupts remain pending until the I2C/SPI interrupt vectors are enabled. Their
respective interrupt service routines are entered shortly thereafter. The RTC interrupts are driven by the alarm and interval flags. Pending RTC interrupts can be cleared without entering the interrupt service routine, by clearing the corresponding RTC flag in software. Entering the interrupt service routine alone does not clear the RTC interrupt. Figure 67 shows how the interrupts are cleared when the interrupt service routines are entered. Some interrupts with multiple interrupt sources are not automatically cleared; specifically, the PSM, ADE, UART, UART2 and Timer 2 interrupt vectors. Note that the INT0 and INT1 interrupts are only cleared if the external interrupt is configured to be triggered by a falling edge by setting IT0 in the Timer/Counter 0 and Timer/Counter 1 control SFR (TCON, 0x88). If INT0 or INT1 is configured to interrupt on a low level, the interrupt service routine is reentered until the respective pin goes high.
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ADE5166/ADE5169/ADE5566/ADE5569
IE/IEIP2 REGISTERS PSM IPSMF IPSME FPSM (IPSMF.6) IP/IEIP2 REGISTERS
Preliminary Technical Data
PRIORITY LEVEL LOW HIGH HIGHEST
RTC
MIDNIGHT ALARM
ADE
MIRQSTH MIRQENH
MIRQSTM MIRQENM
MIRQSTL MIRQENL
MIRQSTL.7
WATCHDOG
WATCHDOG TIMEOUT WDIR
TEMP ADC
TEMPADC INTERRUPT
IN/OUT LATCH RESET
EXTERNAL INTERRUPT 0
INT0
IT0 0 1 IT0
PSM2 IE0
TIMER 0
TF0
INTERRUPT POLLING SEQUENCE
EXTERNAL INTERRUPT 1
IT1 INT1 0 1 IT1
PSM2 IE1
TF1 TIMER 1
SPI INTERRUPT CFG.5 I2C/SPI
1 0
I2C INTERRUPT
IN/OUT LATCH RESET
UART
RI TI RI2 TI2
UART2
TIMER 2
TF2 EXF2
INDIVIDUAL INTERRUPT ENABLE GLOBAL INTERRUPT ENABLE (EA)
LEGEND AUTOMATIC CLEAR SIGNAL
07411-064
Figure 67. Interrupt System Functional Block Diagram
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Preliminary Technical Data
INTERRUPT VECTORS
When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off the stack by a RETI instruction. This allows program execution to resume from where it was interrupted. The interrupt vector addresses are shown in Table 77.
Table 77. Interrupt Vector Addresses
Source IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 ITEMP (Temperature ADC) ISPI/I2CI IPSM (Power Supply) IADE (Energy Measurement DSP) IRTC (RTC Interval Timer) WDT (Watchdog Timer) RI2 + TI2 Vector Address 0x0003 0x000B 0x0013 0x001B 0x0023 0x002B 0x0033 0x003B 0x0043 0x004B 0x0053 0x005B 0x0063
ADE5166/ADE5169/ADE5566/ADE5569
CONTEXT SAVING
When the 8052 vectors to an interrupt, only the program counter is saved on the stack. Therefore, the interrupt service routine must be written to ensure that registers used in the main program are restored to their pre-interrupt state. Common registers that can be modified in the ISR are the accumulator register and the PSW register. Any general-purpose registers that are used as scratch pads in the ISR should also be restored before exiting the interrupt. The following example 8052 code shows how to restore some commonly used registers:
GeneralISR: ; save the current Accumulator value PUSH ACC ; save the current status and register bank selection PUSH PSW
; service interrupt ... ; restore the status and register bank selection POP PSW ACC ; restore the accumulator POP RETI
INTERRUPT LATENCY
The 8052 architecture requires that at least one instruction execute between interrupts. To ensure this, the 8052 MCU core hardware prevents the program counter from jumping to an ISR immediately after completing a RETI instruction or an access of the IP and IE registers. The shortest interrupt latency is 3.25 instruction cycles, 800 ns with a clock of 4.096 MHz. The longest interrupt latency for a high priority interrupt results when a pending interrupt is generated during a low priority interrupt RETI, followed by a multiply instruction. This results in a maximum interrupt latency of 16.25 instruction cycles, 4 s with a clock of 4.096 MHz.
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ADE5166/ADE5169/ADE5566/ADE5569 WATCHDOG TIMER
The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE5166/ADE5169/ ADE5566/ADE5569 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by default with a timeout of two seconds and creates a system reset if not cleared within two seconds. The watchdog function can be disabled by clearing the watchdog enable bit (WDE) in the watchdog timer SFR (WDCON, 0xC0). The watchdog circuit generates a system reset or interrupt (WDS) if the user program fails to set the WDE bit within a predetermined amount of time (set by the PRE[3:0] bits). The watchdog timer is clocked from the 32.768 kHz external crystal connected between the XTAL1 and XTAL2 pins.
Table 78. Watchdog Timer SFR (WDCON, 0xC0)
Bit 7 to 4 Address 0xC7 to 0xC4 Mnemonic PRE[3:0] Default 7
Preliminary Technical Data
The WDCON SFR can be written only by user software if the double write sequence described in Table 78 is initiated on every write access to the WDCON SFR. To prevent any code from inadvertently disabling the watchdog, a watchdog protection can be activated. This watchdog protection locks in the watchdog enable and event settings so they cannot be changed by user code. The protection is activated by clearing a watchdog protection bit in the flash memory. The watchdog protection bit is the most significant bit at Address 0x3FFA of the flash memory. When this bit is cleared, the WDIR bit is forced to 0, and the WDE bit is forced to 1. Note that the sequence for configuring the flash protection bits must be followed to modify the watchdog protection bit at Address 0x3FFA (see the Protecting the Flash section).
Description Watchdog prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input clock (32.768 kHz). The PREx bits set which of the upper bits of the counter are used as the watchdog output as follows:
tWATCHDOG = 2 PRE x 29 XTAL1
3
0xC3
WDIR
0
2
0xC2
WDS
0
PRE[3:0] Result (Watchdog Timeout) 0000 15.6 ms 0001 31.2 ms 0010 62.5 ms 0011 125 ms 0100 250 ms 0101 500 ms 0110 1 sec 0111 2 sec 1000 0 sec, automatic reset 1001 0 sec, serial download reset 1010 to 1111 Not a valid selection Watchdog interrupt response bit. When cleared, the watchdog generates a system reset when the watchdog timeout period has expired. When set, the watchdog generates an interrupt when the watchdog timeout period has expired. Watchdog status bit. This bit is set to indicate that a watchdog timeout has occurred. It is cleared by writing a 0 or by an external hardware reset. A watchdog reset does not clear WDS; therefore, it can be used to distinguish between a watchdog reset and a hardware reset from the RESET pin. Watchdog enable bit. When set, this bit enables the watchdog and clears its counter. The watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is not cleared within its selected timeout period, it generates a system reset or watchdog interrupt, depending on the WDIR bit. Watchdog write enable bit (see the Writing to the Watchdog Timer SFR (WDCON, 0xC0) section).
1
0xC1
WDE
1
0
0xC0
WDWR
0
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Preliminary Technical Data
Bit 7 Mnemonic WDPROT_PROTKY7 Default 1
ADE5166/ADE5169/ADE5566/ADE5569
Table 79. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA)
Description This bit holds the protection for the watchdog timer and the 7th bit of the flash protection key. When this bit is cleared, the watchdog enable and event bits WDE and WDIR cannot be changed by user code. The watchdog configuration is then fixed to WDIR = 0 and WDE = 1. The watchdog timeout in PRE[3:0] can still be modified by user code. The value of this bit is also used to set the flash protection key. If this bit is cleared to protect the watchdog, then the default value for the flash protection key is 0x7F instead of 0xFF (see the Protecting the Flash section for more information on how to clear this bit). These bits hold the flash protection key. The content of this flash address is compared to the flash protection key SFR (PROTKY, 0xBB) when the protection is being set or changed. If the two values match, the new protection is written to the flash Address 0x3FFF to Address 0x3FFB. See the Protecting the Flash section for more information on how to configure these bits.
6 to 0
PROTKY[6:0]
0xFF
Writing to the Watchdog Timer SFR (WDCON, 0xC0)
Writing data to the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the following instruction must be a write instruction to the WDCON SFR.
Disable Watch dog CLR EA SETB WDWR CLR WDE SETB EA
Watchdog Timer Interrupt
If the watchdog timer is not cleared within the watchdog timeout period, a system reset occurs unless the watchdog timer interrupt is enabled. The watchdog timer interrupt response bit (WDIR) is located in the watchdog timer SFR (WDCON, 0xC0). Enabling the WDIR bit allows the program to examine the stack or other variables that may have led the program to execute inappropriate code. The watchdog timer interrupt also allows the watchdog to be used as a long interval timer. Note that WDIR is automatically configured as a high priority interrupt. This interrupt cannot be disabled by the EA bit in the IE register (see Table 71). Even if all of the other interrupts are disabled, the watchdog is kept active to watch over the program.
This sequence is necessary to protect the WDCON SFR from code execution upsets that may unintentionally modify this SFR. Interrupts should be disabled during this operation due to the consecutive instruction cycles.
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ADE5166/ADE5169/ADE5566/ADE5569 LCD DRIVER
Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 x 4 segments without compromising any ADE5166/ADE5169/ADE5566/ADE5569 functions. It is capable of driving LCDs with 2x, 3x, and 4x multiplexing. The LCD waveform voltages generated through internal charge pump circuitry support up to 5 V LCDs. An external resistor ladder for LCD waveform voltage generation is also supported. Each ADE5166/ADE5169/ADE5566/ADE5569 has an embedded LCD control circuit, driver, and power supply circuit. The LCD module is functional in all operating modes (see the Operating Modes section) and can store up to four different screens in memory for scrolling purposes.
Table 80. LCD Driver SFRs
SFR Address 0x95 0x96 0x97 0x9C 0xAC 0xAE 0xB1 0xED R/W R/W R/W R/W R/W R/W R/W R/W R/W Mnemonic LCDCON LCDCLK LCDSEGE LCDCONX LCDPTR LCDDAT LCDCONY LCDSEGE2 Description LCD configuration (see Table 81). LCD clock (see Table 85). LCD segment enable (see Table 88). LCD Configuration X (see Table 82). LCD pointer (see Table 89). LCD data (see Table 90). LCD Configuration Y (see Table 84). LCD Segment Enable 2 (see Table 91).
Preliminary Technical Data
LCD REGISTERS
There are six LCD control registers that configure the driver for the specific type of LCD in the end system and set up the user display preferences. The LCD configuration SFR (LCDCON, 0x95), LCD Configuration X SFR (LCDCONX, 0x9C), and LCD Configuration Y SFR (LCDCONY, 0xB1) contain general LCD driver configuration information including the LCD enable and reset, as well as the method of LCD voltage generation and multiplex level. The LCD clock SFR (LCDCLK, 0x96) configures timing settings for LCD frame rate and blink rate. LCD pins are configured for LCD functionality in the LCD segment enable SFR (LCDSEGE, 0x97) and the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED).
Table 81. LCD Configuration SFR (LCDCON, 0x95)
Bit 7 6 5 4 Mnemonic LCDEN LCDRST BLINKEN LCDPSM2 Value 0 0 0 0 Description LCD enable. If this bit is set, the LCD driver is enabled. LCD data registers reset. If this bit is set, the LCD data registers are reset to zero. Blink mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD clock SFR (LCDCLK, 0x96). Forces LCD off when in PSM2 (sleep mode). Note that the internal voltage reference must be enabled by setting the REF_BAT_EN bit in the peripheral configuration SFR (PERIPH, 0xF4) to allow LCD operation in PSM2. LCDPSM2 Result 0 The LCD is disabled or enabled in PSM2 by the LCDEN bit. 1 The LCD is disabled in PSM2 regardless of LCDEN setting. LCD clock selection. CLKSEL Result 0 fLCDCLK = 2048 Hz 1 fLCDCLK = 128 Hz Bias mode. BIAS Result 0 1/2 1 1/3 LCD multiplex level. LMUX[1:0] Result 00 Reserved. 01 2x Multiplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as FP28. 10 3x Multiplexing. FP27/COM3 is used as FP27. FP28/COM2 is used as COM2. 11 4x Multiplexing. FP27/COM3 is used as COM3. FP28/COM2 is used as COM2.
3
CLKSEL
0
2
BIAS
0
1 to 0
LMUX[1:0]
0
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Preliminary Technical Data
Table 82. LCD Configuration X SFR (LCDCONX, 0x9C)
Bit 7 6 Mnemonic Reserved EXTRES Default 0 0
ADE5166/ADE5169/ADE5566/ADE5569
5 to 0
BIASLVL[5:0]
0
Description Reserved. External resistor ladder selection bit. EXTRES Result 0 External resistor ladder is disabled. Charge pump is enabled. 1 External resistor ladder is enabled. Charge pump is disabled. Bias level selection bits (see Table 83).
Table 83. LCD Bias Voltage When Contrast Control Is Enabled
BIASLVL[5] 0 1 VA (V) VREF x BIASLVL[4:0 ] 31 VB VB = VA VB = VA 1/2 Bias VC VC = 2 x VA VC = 2 x VA VB VB = 2 x VA VB = 2 x VA 1/3 Bias VC VC = 3 x VA VC = 3 x VA
BIASLVL[4:0 ] VREF x 1 + 31
Table 84. LCD Configuration Y SFR (LCDCONY, 0xB1)
Bit 7 Mnemonic AUTOSCREENSCROLL Default 0 Description When set, the four screens scroll automatically. The scrolling item is selected by the BLKFREQ bits in the LCD clock SFR (LCDCLK, 0x96). If both BLINKEN and this bit are set, this bit preempt the blinking mode. Frame inversion mode enable bit. If this bit is set, frames are inverted every other frame. If this bit is cleared, frames are not inverted. These bits should be kept cleared for proper operation. These bits select the screen that is being output on the LCD pins. Values of 0, 1, 2, and 3 select screen 0, 1, 2, and 3, respectively Update finished flag bit. This bit is updated by the LCD driver. When set, this bit indicates that the LCD memory has been updated and a new frame has begun. Refresh LCD data memory bit. This bit should be set by the user. When set, the LCD driver does not use the data in the LCD data registers to update the display. The LCD data registers can be updated by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display at the next frame.
6 5 to 4 3 to 2 1 0
INV_LVL Reserved SCREEN_SEL UPDATEOVER REFRESH
0 00
0 0
Table 85. LCD Clock SFR (LCDCLK, 0x96)
Bit 7 to 6 Mnemonic BLKMOD[1:0] Default 0 Description Blink mode clock source configuration bits. BLKMOD[1:0] Result 00 The blink rate is controlled by software. The display is off. 01 The blink rate is controlled by software. The display is on. 10 The blink rate is 2 Hz. 11 The blink rate is set by BLKFREQ[1:0]. Blink rate configuration bits. These bits control the LCD blink rate if BLKMOD[1:0] = 11. BLKFREQ[1:0] Result (Blink Rate) 00 1 Hz 01 1/2 Hz 10 1/3 Hz 11 1/4 Hz LCD frame rate selection bits (see Table 86 and Table 87).
5 to 4
BLKFREQ[1:0]
0
3 to 0
FD[3:0]
0
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ADE5166/ADE5169/ADE5566/ADE5569
Table 86. LCD Frame Rate Selection for fLCDCLK = 2048 Hz (LCDCON[3] = 0)
FD3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
1
Preliminary Technical Data
3x Multiplexing fLCD (Hz) Frame Rate (Hz) 341.3 170.71 341.3 113.81 256 85.3 204.8 68.3 170.7 56.9 146.3 48.8 128 42.7 113.8 37.9 102.4 34.1 93.1 31 85.3 28.4 78.8 26.3 73.1 24.4 68.3 22.8 64 21.3 32 10.7 4x Multiplexing fLCD (Hz) Frame Rate (Hz) 512 1281 341.3 85.3 256 64 204.8 51.2 170.7 42.7 146.3 36.6 128 32 113.8 28.5 102.4 25.6 93.1 23.25 85.3 21.35 78.8 19.7 73.1 18.3 68.3 17.05 64 16 32 8
FD2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
FD1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
FD0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
2x Multiplexing fLCD (Hz) Frame Rate (Hz) 256 1281 170.7 85.3 128 64 102.4 51.2 85.3 42.7 73.1 36.6 64 32 56.9 28.5 51.2 25.6 46.5 23.25 42.7 21.35 39.4 19.7 36.6 18.3 34.1 17.05 32 16 16 8
Not within the range of typical LCD frame rates.
Table 87. LCD Frame Rate Selection for fLCDCLK = 128 Hz (LCDCON[3] = 1)
FD3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
1
FD2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
FD1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
FD0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
2x Multiplexing fLCD (Hz) Frame Rate (Hz) 32 161 21.3 10.6 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 16 8 128 64 64 32
3x Multiplexing fLCD (Hz) Frame Rate (Hz) 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 32 10.7 128 42.7 64 21.3
4x Multiplexing fLCD (Hz) Frame Rate (Hz) 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 32 8 128 32 64 16
Not within the range of typical LCD frame rates.
Table 88. LCD Segment Enable SFR (LCDSEGE, 0x97)
Bit 7 6 5 4 3 2 1 to 0 Mnemonic FP25EN FP24EN FP23EN FP22EN FP21EN FP20EN Reserved Default 0 0 0 0 0 0 0 Description FP25 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP24 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP23 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP22 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP21 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP20 function select bit. 0 = general-purpose I/O, 1 = LCD function. These bits should be left at 0 for proper operation.
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Preliminary Technical Data
Table 89. LCD Pointer SFR (LCDPTR, 0xAC)
Bit 7 6 5 to 4 3 to 0 Mnemonic R/W Reserved RAM2SCREEN ADDRESS Default 0 0 0 0
ADE5166/ADE5169/ADE5566/ADE5569
Description Read or write LCD bit. If this bit is set (1), the data in LCDDAT is written to the address indicated by the LCDPTR[3:0] bits. Reserved. These bits select the screen recipient of the data memory action. LCD memory address (see Table 92).
Table 90. LCD Data SFR (LCDDAT, 0xAE)
Bit 7 to 0 Mnemonic LCDDATA Default 0 Description Data to be written into or read out of the LCD memory SFRs.
Table 91. LCD Segment Enable 2 SFR (LCDSEGE2, 0xED)
Bit 7 to 4 3 2 1 0 Mnemonic Reserved FP19EN FP18EN FP17EN FP16EN Default 0 0 0 0 0 Description Reserved. FP19 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP18 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP17 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP16 function select bit. 0 = general-purpose I/O, 1 = LCD function.
LCD SETUP
The LCD configuration SFR (LCDCON, 0x95) configures the LCD module to drive the type of LCD in the user end system. The BIAS and LMUX[1:0] bits in this SFR should be set according to the LCD specifications. The COM2/FP28 and COM3/FP27 pins default to LCD segment lines. Selecting the 3x multiplex level in the LCD configuration SFR (LCDCON, 0x95) by setting LMUX[1:0] to 10 changes the FP28 pin functionality to COM2. The 4x multiplex level selection, LMUX[1:0] = 11, changes the FP28 pin functionality to COM2 and the FP27 pin functionality to COM3. The LCD segments, FP0 to FP15 and FP26, are enabled by default. Additional pins are selected for LCD functionality in the LCD segment enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED) where there are individual enable bits for the FP16 to FP25 segment pins. The LCD pins do not have to be enabled sequentially. For example, if the alternate function of FP23, the Timer 2 input, is required, any of the other shared pins, FP16 to FP25, can be enabled instead. The Display Element Control section contains details about setting up the LCD data memory to turn individual LCD segments on and off. Setting the LCDRST bit in the LCD configuration SFR (LCDCON, 0x95) resets the LCD data memory to its default (0). A power-on reset also clears the LCD data memory.
LCD TIMING AND WAVEFORMS
An LCD segment acts like a capacitor that is charged and discharged at a certain rate. This rate, the refresh rate, determines the visual characteristics of the LCD. A slow refresh rate results in the LCD blinking on and off between refreshes. A fast refresh rate presents a screen that appears to be continuously lit. In addition, a faster refresh rate consumes more power. The frame rate, or refresh rate, for the LCD module is derived from the LCD clock, fLCDCLK. The LCD clock is selected as 2048 Hz or 128 Hz by the CLKSEL bit in the LCD configuration SFR (LCDCON, 0x95). The minimum refresh rate needed for the LCD to appear solid (without blinking) is independent of the multiplex level. The LCD waveform frequency, fLCD, is the frequency at which the LCD switches the active common line. Thus, the LCD waveform frequency depends heavily on the multiplex level. The frame rate and LCD waveform frequency are set by fLCDCLK, the multiplex level, and the FD[3:0] frame rate selection bits in the LCD clock SFR (LCDCLK, 0x96). The LCD module provides 16 different frame rates for fLCDCLK = 2048 Hz, ranging from 8 Hz to 128 Hz for an LCD with 4x multiplexing. Fewer options are available with fLCDCLK = 128 Hz, ranging from 8 Hz to 32 Hz for a 4x multiplexed LCD. The 128 Hz clock is beneficial for battery operation because it consumes less power than the 2048 Hz clock. The frame rate is set by the FD[3:0] bits in the LCD clock SFR (LCDCLK, 0x96); see Table 86 and Table 87. The LCD waveform is inverted at twice the LCD waveform frequency, fLCD. This way, each frame has an average dc offset of zero. ADC offset degrades the lifetime and performance of the LCD.
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ADE5166/ADE5169/ADE5566/ADE5569
BLINK MODE
Blink mode is enabled by setting the BLINKEN bit in the LCD configuration SFR (LCDCON, 0x95). This mode is used to alternate between the LCD on state and LCD off state so that the LCD screen appears to blink. There are two blinking modes: a software controlled blink mode and an automatic blink mode.
Preliminary Technical Data
and the MSBs store the state of the odd numbered segment lines. For example, LCD Data Address 0 refers to segment Line 1 and Line 0 (see Table 92). Note that the LCD data memory is maintained in the PSM2 operating mode. The LCD data memory is accessed indirectly through the LCD pointer SFR (LCDPTR, 0xAC) and LCD data SFR (LCDDAT, 0xAE). Moving a value to the LCDPTR SFR selects the LCD screen and data byte to be accessed and initiates a read or write operation (see Table 89).
Software Controlled Blink Mode
The LCD blink rate can be controlled by user code with the BLKMOD[1:0] bits in the LCD clock SFR (LCDCLK, 0x96) by toggling the bits to turn the display on and off at a rate determined by the MCU code.
Writing to LCD Data Registers
To update the LCD data memory, first set the LSB of the LCD Configuration Y SFR (LCDCONY, 0xB1) to freeze the data being displayed on the LCD while updating it. This operation ensures that the data displayed on the screen does not change while the data is being changed. Then, move the data to the LCD data SFR (LCDDAT, 0xAE) prior to accessing the LCD pointer SFR (LCDPTR, 0xAC). The address of the LCD screen should be consistent with the data changed. When the MSB of the LCD pointer SFR (LCDPTR, 0xAC) is set, the content of the LCD data SFR (LCDDAT, 0xAE) is transferred to the internal LCD data memory designated by the address in the LCD pointer SFR (LCDPTR, 0xAC) and the screen designator. Clear the LSB of the LCD Configuration Y SFR (LCDCONY, 0xB1) when all of the data memory has been updated to allow the use of the new LCD setup for display. Sample 8052 code to update the segments attached to Pin FP10 and Pin FP11 on Screen 1 is as follows:
ORL MOV MOV ANL LCDCONY,#01h ;start updating the data LCDDAT,#FFh LCDPTR,#80h OR 05h LCDCONY,#0FEh ;update finished
Automatic Blink Mode
There are five blink rates. These blink rates are selected by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD clock SFR (LCDCLK, 0x96); see Table 85.
SCROLLING MODE
The ADE5166/ADE5169/ADE5566/ADE5569 provide the possibility to have four screens in memory. The LCD driver can use any of these screens by setting the SCREEN_SEL bits in the LCD Configuration Y SFR (LCDCONY, 0xB1) and clearing the refresh bit in the same register. The software scrolling of the screens can then be achieved by a one-command instruction.
Automatic Scrolling Mode
The ADE5166/ADE5169/ADE5566/ADE5569 also provide an automatic scrolling between the screens using the five blink rates available. This mode is enabled by setting bit AUTOSCREENSCROLL in the LCD Configuration Y SFR (LCDCONY, 0xB1) and also the BLINKEN bit in the LCD configuration SFR (LCDCON 0x95). To allow the scrolling frequency to be selected, the BLKMOD[1:0] bits in the LCD Clock register (LCDCLK, 0x96) should both be set to 1. The scrolling rates are then selected by the BLKFREQ[1:0] bits in the LCD Clock register (LCDCLK, 0x96); see Table 85. Automatic scrolling mode is available in all operating modes.
Reading LCD Data Registers
When the MSB of the LCD pointer SFR (LCDPTR, 0xAC) is cleared, the content of the LCD data memory of the corresponding screen designated by LCDPTR is transferred to the LCD data SFR (LCDDAT, 0xAE). Sample 8052 code to read the contents of LCD Data Memory Address 0x07 on Screen 1, which holds the on and off state of the segments attached to FP14 and FP15, is as follows.
MOV MOV LCDPTR,#07h R1, LCDDAT
DISPLAY ELEMENT CONTROL
Four banks of 15 bytes of data memory located in the LCD module controls the on or off state of each segment of the LCD. The LCD data memory is stored in Address 0 through Address 14 in the LCD module with two extra bits defining which one of the four screen is being addressed. Each byte configures the on and off states of two segment lines. The LSBs store the state of the even numbered segment lines
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Preliminary Technical Data
LCD Pointer SFR (LCDPTR, 0xAC) COM2 COM1 COM0 FP27 FP25 FP23 FP21 FP19 FP17 FP15 FP13 FP11 FP9 FP7 FP5 FP3 FP1 FP27 FP25 FP23 FP21 FP19 FP17 FP15 FP13 FP11 FP9 FP7 FP5 FP3 FP1 FP27 FP25 FP23 FP21 FP19 FP17 FP15 FP13 FP11 FP9 FP7 FP5 FP3 FP1
ADE5166/ADE5169/ADE5566/ADE5569
LCD Pointer SFR (LCDDAT, 0xAE) COM2 COM1 COM0 FP28 FP28 FP28 FP26 FP26 FP26 FP24 FP24 FP24 FP22 FP22 FP22 FP20 FP20 FP20 FP18 FP18 FP18 FP16 FP16 FP16 FP14 FP14 FP14 FP12 FP12 FP12 FP10 FP10 FP10 FP8 FP8 FP8 FP6 FP6 FP6 FP4 FP4 FP4 FP2 FP2 FP2 FP0 FP0 FP0
Table 92. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, 0xAC) and LCD Data SFR (LCDDAT, 0xAE)1, 2
LCD Memory Address 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
1 2
COM3 FP27 FP25 FP23 FP21 FP19 FP17 FP15 FP13 FP11 FP9 FP7 FP5 FP3 FP1
COM3 FP28 FP26 FP24 FP22 FP20 FP18 FP16 FP14 FP12 FP10 FP8 FP6 FP4 FP2 FP0
COMx designates the common lines. FPx designates the segment lines.
VOLTAGE GENERATION
The ADE5166/ADE5169/ADE5566/ADE5569 provide two ways to generate the LCD waveform voltage levels. The on-chip charge pump option can generate 5 V. This makes it possible to use 5 V LCDs with the 3.3 V ADE5166/ADE5169/ADE5566/ ADE5569. There is also an option to use an external resistor ladder with a 3.3 V LCD. The EXTRES bit in the LCD Configuration X SFR (LCDCONX, 0x9C) selects the resistor ladder or charge pump option. When selecting how to generate the LCD waveform voltages, the following should be considered: * * Lifetime performance power consumption Contrast control
ADE5569 temperature and supply voltage measurements (see the Temperature, Battery, and Supply Voltage Measurements section). This dynamic contrast control is not easily implemented with external resistor ladder voltage generation. The LCD bias voltage sets the contrast of the display when the charge pump provides the LCD waveform voltages. The ADE5166/ ADE5169/ADE5566/ADE5569 provide 64 bias levels selected by the BIASLVL bits in the LCD Configuration X SFR (LCDCONX, 0x9C). The voltage level on LCDVA, LCDVB and LCDVC depend on the internal voltage reference value (VREF), BIASLVL[5:0] selection, and the biasing selected as described in Table 83.
Lifetime Performance
DC offset on a segment degrades its performance over time. The voltages generated through the internal charge pump switch faster than those generated by the external resistor ladder, reducing the likelihood of a dc voltage being applied to a segment and increasing the lifetime of the LCD.
Lifetime Performance Power Consumption
In most LCDs, a high amount of current is required when the LCD waveforms change state. The external resistor ladder option draws a constant amount of current, whereas the charge pump circuitry allows dynamic current consumption. If the LCD module is used with the internal charge pump option when the display is disabled, the voltage generation is disabled, so that no power is consumed by the LCD function. This feature results in significant power savings if the display is turned off during battery operation.
LCD EXTERNAL CIRCUITRY
The voltage generation selection is made by Bit EXTRES in the LCD Configuration X SFR (LCDCONX, 0x9C). This bit is cleared by default for charge pump voltage generation, but can be set to enable an external resistor ladder.
Contrast Control
The electrical characteristics of the liquid in the LCD change over temperature. This requires adjustments in the LCD waveform voltages to ensure a readable display. An added benefit of the internal charge pump voltage generation is a configurable bias voltage that can be compensated over temperature and supply to maintain contrast on the LCD. These compensations can be performed based on the ADE5166/ADE5169/ADE5566/
Charge Pump
Voltage generation through the charge pump requires external capacitors to store charge. The external connections to LCDVA, LCDVB, and LCDVC, as well as LCDVP1 and LCDVP2, are shown in Figure 68.
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LCDVC CHARGE PUMP AND LCD WAVEFORM CIRCUITRY LCDVB LCDVA LCDVP1 LCDVP2 100nF 470nF
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Preliminary Technical Data
A 96-segment LCD with 4x multiplexing requires 96/4 = 24 segment lines. Sixteen pins, FP0 to FP15, are automatically dedicated for use as LCD segments. Eight more pins must be chosen for the LCD function. Because the LCD has 4x multiplexing, all four common lines are used. As a result, COM2/FP28 and COM3/FP27 cannot be used as segment lines. Based on the alternate functions of the pins used for FP16 through FP25, FP16 to FP23 are chosen for the eight remaining segment lines. These pins are enabled for LCD functionality in the LCD segment enable SFR (LCDSEGE, 0x97) and LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). To determine contrast setting for this 5 V LCD, Table 83 shows the BIASLVL[5:0] setting that corresponds to a VC of 5 V in 1/3 bias mode. The maximum bias level setting for this LCD is BIASLVL[5:0] = 101110. The LCD is set up with the following 8052 code:
; set up LCD pins to have LCD functionality MOV MOV LCDSEG,#FP20EN+FP21EN+FP22EN+FP23EN LCDSEGX,#FP16EN+FP17EN+FP18EN+FP19EN
470nF 470nF
Figure 68. External Circuitry for Charge Pump Option
External Resistor Ladder
To enable the external resistor ladder option, set the EXTRES bit in the LCD Configuration X SFR (LCDCONX, 0x9C). When EXTRES = 1, the LCD waveform voltages are supplied by the external resistor ladder. Because the LCD voltages are not generated on-chip, the LCD bias compensation implemented to maintain contrast over temperature and supply is not possible. The external circuitry needed for the resistor ladder option is shown in Figure 69. The resistors required should be in the range of 10 k to 100 k and based on the current required by the LCD being used.
LCDVC LCD WAVEFORM CIRCUITRY LCDVB LCDVA
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LCDVP1 LCDVP2
; set up LCDCON for fLCDCLK=2048Hz, 1/3 bias and 4x multiplexing MOV LCDCON,#BIAS+LMUX1+LMUX0 ; set up LCDCONX for charge pump and BIASLVL[110111] MOV LCDCONX,#BIASLVL5+BIASLVL4+BIASLVL3+BI ASLVL2+BIASLVL1+BIASLVL0 ; set up refresh rate for 64Hz with fLCDCLK = 2048 Hz MOV LCDCLK,#FD3+FD2+FD1+FD0 ; set up LCD data registers with data to be displayed using ; LCDPTR and LCDDATA registers ; turn all segments on FP27 ON and FP26 OFF ORL LCDCONY,#01h ; start data memory refresh MOV MOV LCDDAT,#F0H LCDPTR, #80h OR 0DH
Figure 69. External Circuitry for External Resistor Ladder Option
LCD FUNCTION IN PSM2
The LCDPSM2 and LCDEN bits in the LCD configuration SFR (LCDCON, 0x95) control LCD functionality in the PSM2 operating mode (see Table 93). Note that the internal voltage reference must be enabled by setting the REF_BAT_EN bit in the peripheral configuration SFR (PERIPH, 0xF4) to allow LCD operation in PSM2 (see Table 19).
Table 93. Bits Controlling LCD Functionality in PSM2 Mode
LCDPSM2 0 0 1 LCDEN 0 1 X Result The display is off in PSM2. The display is on in PSM2. The display is off in PSM2.
In addition, note that the LCD configuration and data memory is retained when the display is turned off.
ANL LCDCONY,#0FEh ; end of data memory refresh ORL LCDCON,#LCDEN ; enable LCD
Example LCD Setup
An example of how to set up the LCD peripheral for a specific LCD is described in this section with the following parameters: * * * Type of LCD: 5 V, 4x multiplexed with 1/3 bias, 96 segment Voltage generation: internal charge pump Refresh rate: 64 Hz
To set up the same 3.3 V LCD for use with an external resistor ladder,
; setup LCDCONX for external resistor ladder MOV LCDCONX,#EXTRES
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Preliminary Technical Data FLASH MEMORY
FLASH MEMORY OVERVIEW
Flash memory is a type of nonvolatile memory that is in-circuit programmable. The default, erased state of a byte of flash memory is 0xFF. When a byte of flash memory is programmed, the required bits change from one to zero. The flash memory must be erased to turn the zeros back to ones. A byte of flash memory cannot however be erased individually. The entire segment, or page, of flash memory that contains the byte must be erased. The ADE5166/ADE5169/ADE5566/ADE5569 provide 62 bytes of flash program/information memory. This memory is segmented into 124 pages each containing 512 bytes. To reprogram one byte of flash memory, the 511 bytes in that page must be erased. The flash memory can be erased by page or all at once in a mass erase. There is a command to verify that a flash write operation has completed successfully. The ADE5166/ADE5169/ADE5566/ ADE5569 flash memory controller also offers configurable flash memory protection. The 62 bytes of flash memory are provided on-chip to facilitate code execution without any external discrete ROM device requirements. The program memory can be programmed incircuit, using the serial download mode provided or using conventional third party memory programmers.
ADE5166/ADE5169/ADE5566/ADE5569
Retention is the ability of the Flash memory to retain its programmed data over time. Again, the parts have been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 55C). As part of this qualification procedure, the flash memory is cycled to its specified endurance limit described previously, before data retention is characterized. This means that the flash memory is guaranteed to retain its data for its full specified retention lifetime every time the flash memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, derates with TJ, as shown in Figure 70.
300
250
RETENTION (Years)
200
150
ANALOG DEVICES SPECIFICATION 100 YEARS MIN. AT TJ = 55C
100
50
50
60 70 90 80 TJ JUNCTION TEMPERATURE (C)
100
110
Flash/EE Memory Reliability
The flash memory arrays on the ADE5166/ADE5169/ADE5566/ ADE5569 are fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events: 1. 2. 3. 4. Initial page erase sequence Read/verify sequence Byte program sequence Second read/verify sequence
Figure 70. Flash/EE Memory Data Retention
FLASH MEMORY ORGANIZATION
The ADE5166/ADE5169/ADE5566/ADE5569 contain a 64 kB array of Flash/EE program memory. The upper 2 kB contain permanently embedded firmware, allowing in-circuit serial download, serial debug and nonintrusive single-pin emulation. The 2 kB of embedded firmware also contains essential coefficients that provide calibration to peripherals such as the ADCs and reference. The embedded firmware contained in the upper 2 kB of Flash/EE memory is not accessible by the user.
EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 kB OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS NOP INSTRUCTIONS TO USER CODE. 0xFFFF 2kB 0xF800
In reliability qualification, every byte in both the program and data Flash/EE memory is cycled from 0x00 to 0xFF until a first fail is recorded, signifying the endurance limit of the on-chip Flash/EE memory. As indicated in Table 4, the ADE5166/ADE5169/ADE5566/ ADE5569 flash memory endurance qualification has been carried out in accordance with JEDEC Standard Method A117 over the industrial temperature range of -40C, +25C, and +85C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with a minimum endurance figure of 20,000 cycles of operation at 25C.
USER PROGRAM MEMORY 62 kB OF FLASH/EE PROGRAM MEMORY ARE AVAILABLE TO THE USER. ALL OF THIS SPACE CAN BE PROGRAMMED FROM THE PERMANENTLY EMBEDDED DOWNLOAD/DEBUG KERNEL OR IN PARALLEL PROGRAMMING MODE. 0xF7FF 62kB 0x0000
Figure 71. Flash Memory Organization
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0 40
ADE5166/ADE5169/ADE5566/ADE5569
The lower 62 bytes are available to the user for program storage or as nonvolatile data memory. They are segmented into 124 pages of 512 bytes each. It is up to the user to decide which flash memory is to be used for data memory. It is recommended that each page be dedicated solely to program or data memory so that an instance does not arise where the program counter is loaded with data memory instead of an opcode from the program memory or where program memory is erased to update a byte of data memory. The flash memory can be protected from read or write/erase access. The protection is implemented in the upper page of user program memory. The last sixteen bytes from this page are used to configure the write/erase protection for each of the pages. The remaining four bytes are used for configuring read protection of the flash memory. The read protection is selected in groups of four pages. Finally, there is a byte used to store the key required for modifying the protection scheme. If any code protection is required, the page of information memory must be write/erase protected at a minimum. Thus it is recommended that if code protection is enabled, the last page of user accessible flash memory should only be used to store data that does not need modification in the field. If the firmware requires protection and may need updating in the future, the last page should be reserved for constants used by the user code that does not require modification during emulation or debug. Page 0 through Page 122 are therefore available for general program and data memory use. It is recommended that Page 123 be used for constants or code that do not require future modifications. Note that the last 20 bytes of page 123 are reserved for the flash memory protection and are therefore unavailable to the user.
Preliminary Technical Data
USING THE FLASH MEMORY
The 62 bytes of Flash memory are configured as 124 pages, each of 512 bytes. As with the other ADE5166/ADE5169/ADE5566/ ADE5569 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A data register, EDATA, holds the byte of data to be accessed. The byte of flash memory is addressed via the EADRH and EADRL registers.
Table 94. Flash SFRs
SFR ECON FLSHKY PROTKY EDATA EADRL EADRH Address 0xB9 0xBA 0xBB 0xBC 0xC6 0xC7 Default 0x00 0xFF 0xFF 0x00 0x00 0x00 Bit Addressable No No No No No No Description Flash control Flash key Flash protection key Flash data Flash low address Flash high address
ECON is an 8-bit control register that can be written to with one of five Flash memory access commands to trigger various read, write, erase, and verify functions. Figure 72 demonstrates the steps required for access to the flash memory.
ECON COMMAND ADDRESS EADRH EADRL FLASH PROTECTION KEY FLSHKY ADDRESS DECODER PROTECTION DECODER ACCESS ALLOWED? TRUE: ACCESS ALLOWED ECON = 0
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FLSHKY = 0x3B?
FALSE: ACCESS DENIED ECON = 1
Figure 72. Flash Memory Read/Write/Erase Protection Block Diagram
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Preliminary Technical Data
0xDFFF 0xDE00 0xDDFF 0xDC00 0xDBFF 0xDA00 0xD9FF 0xF7FF 0xF600 0xF5FF 0xF400 0xF3FF 0xF200 0xF1FF 0xF000 0xEFFF 0xEE00 0xEDFF 0xEC00 0xEBFF 0xEA00 0xE9FF 0xE800 0xE7FF 0xE600 0xE5FF 0xE400 0xE3FF 0xE200 0xE1FF 0xE000 PAGE 123 PAGE 122 PAGE 121 PAGE 120 PAGE 119 PAGE 118 PAGE 117 PAGE 116 PAGE 115 PAGE 114 PAGE 113 PAGE 112 READ PROTECT BIT 28 READ PROTECT BIT 30 0xD800 0xD7FF 0xD600 0xD5FF 0xD400 0xD3FF 0xD200 0xD1FF 0xD000 0xCFFF 0xCE00 0xCDFF READ 0xCC00 PROTECT 0xCBFF BIT 29 0xCA00 0xC9FF 0xC800 0xC7FF 0xC600 0xC5FF 0xC400 0xC3FF 0xC200 0xC1FF 0xC000 PAGE 111 PAGE 110 PAGE 109 PAGE 108 PAGE 107 PAGE 106 PAGE 105 PAGE 104 PAGE 103 PAGE 102 PAGE 101 PAGE 100 PAGE 99 PAGE 98 PAGE 97 PAGE 96 READ PROTECT BIT 24 READ PROTECT BIT 25 READ PROTECT BIT 26 READ PROTECT BIT 27 0xBFFF 0xBE00 0xBDFF 0xBC00 0xBBFF 0xBA00 0xB9FF 0xB800 0xB7FF 0xB600 0xB5FF 0xB400 0xB3FF 0xB200 0xB1FF 0xB000 0xAFFF 0xAE00 0xADFF 0xAC00 0xABFF 0xAA00 0xA9FF 0xA800 0xA7FF 0xA600 0xA5FF 0xA400 0xA3FF 0xA200 0xA1FF 0xA000
ADE5166/ADE5169/ADE5566/ADE5569
0x9FFF PAGE 95 PAGE 94 PAGE 93 PAGE 92 PAGE 91 PAGE 90 PAGE 89 PAGE 88 PAGE 87 PAGE 86 PAGE 85 PAGE 84 PAGE 83 PAGE 82 PAGE 81 PAGE 80 READ PROTECT BIT 20 READ PROTECT BIT 21 READ PROTECT BIT 22 READ PROTECT BIT 23 0x9E00 0x9DFF 0x9C00 0x9BFF 0x9A00 0x99FF 0x9800 0x97FF 0x9600 0x95FF 0x9400 0x93FF 0x9200 0x91FF 0x9000 0x8FFF 0x8E00 0x8DFF 0x8C00 0x8BFF 0x8A00 0x89FF 0x8800 0x87FF 0x8600 0x85FF 0x8400 0x83FF 0x8200 0x81FF 0x8000 PAGE 79 PAGE 78 PAGE 77 PAGE 76 PAGE 75 PAGE 74 PAGE 73 PAGE 72 PAGE 71 PAGE 70 PAGE 69 PAGE 68 PAGE 67 PAGE 66 PAGE 65 PAGE 64 READ PROTECT BIT 16 READ PROTECT BIT 17 READ PROTECT BIT 18 READ PROTECT BIT 19
0x7FFF 0x7E00 0x7DFF 0x7C00 0x7BFF 0x7A00 0x79FF 0x7800 0x77FF 0x7600 0x75FF 0x7400 0x73FF 0x7200 0x71FF 0x7000 0x6FFF 0x6E00 0x6DFF 0x6C00 0x6BFF 0x6A00 0x69FF 0x6800 0x67FF 0x6600 0x65FF 0x6400 0x63FF 0x6200 0x61FF 0x6000 PAGE 63 PAGE 62 PAGE 61 PAGE 60 PAGE 59 PAGE 58 PAGE 57 PAGE 56 PAGE 55 PAGE 54 PAGE 53 PAGE 52 PAGE 51 PAGE 50 PAGE 49 PAGE 48 READ PROTECT BIT 12 READ PROTECT BIT 13 READ PROTECT BIT 14 READ PROTECT BIT 15
0x5FFF 0x5E00 0x5DFF 0x5C00 0x5BFF 0x5A00 0x59FF 0x5800 0x57FF 0x5600 0x55FF 0x5400 0x53FF 0x5200 0x51FF 0x5000 0x4FFF 0x4E00 0x4DFF 0x4C00 0x4BFF 0x4A00 0x49FF 0x4800 0x47FF 0x4600 0x45FF 0x4400 0x43FF 0x4200 0x41FF 0x4000
PAGE 47 PAGE 46 PAGE 45 PAGE 44 PAGE 43 PAGE 42 PAGE 41 PAGE 40 PAGE 39 PAGE 38 PAGE 37 PAGE 36 PAGE 35 PAGE 34 PAGE 33 PAGE 32 READ PROTECT BIT 8 READ PROTECT BIT 9 READ PROTECT BIT 10 READ PROTECT BIT 11
0x3FFF 0x3E00 0x3DFF 0x3C00 0x3BFF 0x3A00 0x39FF 0x3800 0x37FF 0x3600 0x35FF 0x3400 0x33FF 0x3200 0x31FF 0x3000 0x2FFF 0x2E00 0x2DFF 0x2C00 0x2BFF 0x2A00 0x29FF 0x2800 0x27FF 0x2600 0x25FF 0x2400 0x23FF 0x2200 0x21FF 0x2000 PAGE 31 PAGE 30 PAGE 29 PAGE 28 PAGE 27 PAGE 26 PAGE 25 PAGE 24 PAGE 23 PAGE 22 PAGE 21 PAGE 20 PAGE 19 PAGE 18 PAGE 17 PAGE 16 READ PROTECT BIT 4 READ PROTECT BIT 5 READ PROTECT BIT 6 READ PROTECT BIT 7
0x1FFF 0x1E00 0x1DFF 0x1C00 0x1BFF 0x1A00 0x19FF 0x1800 0x17FF 0x1600 0x15FF 0x1400 0x13FF 0x1200 0x11FF 0x1000 0x0FFF 0x0E00 0x0DFF 0x0C00 0x0BFF 0x0A00 0x09FF 0x0800 0x07FF 0x0600 0x05FF 0x0400 0x03FF 0x0200 0x01FF 0x0000
PAGE 15 PAGE 14 PAGE 13 PAGE 12 PAGE 11 PAGE 10 PAGE 9 PAGE 8 PAGE 7 PAGE 6 PAGE 5 PAGE 4 PAGE 3 PAGE 2 PAGE 1 PAGE 0 READ PROTECT BIT 0
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READ PROTECT BIT 3
READ PROTECT BIT 2
READ PROTECT BIT 1
CONTAINS PROTECTION SETTINGS
Figure 73. Flash Memory Organization
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ECON--Flash/EE Memory Control SFR
Programming flash memory is done through the flash memory control flash control SFR (ECON, 0xB9). This SFR allows the user to read, write, erase, or verify the 62 kB of flash memory. As a method of security, a key must be written to the FLSHKY register to initiate any user access to the flash memory. Upon completion of the flash memory operation, the FLSHKY register is reset such that it must be written prior to another flash memory operation. Requiring the key to be set before an access to the flash memory decreases the likelihood of user code or data being overwritten by a program that has run amuck.
Table 95. Flash Control SFR (ECON, 0xB9)
Bit 7 to 0 Mnemonic ECON Default 0
Preliminary Technical Data
The program counter, PC, is held on the instruction where the ECON register is written to until the flash memory controller is done performing the requested operation. Then the PC increments to continue with the next instruction. Any interrupts requests that occur while the flash controller is performing an operation are not handled until the flash operation is complete. All peripherals, such as timers and counters, will continue to operate as configured throughout the flash memory access.
Value Description 1 Write byte. The value in EDATA is written to the Flash memory, at the page address given by EADRH and EARDL. Note that the byte being addressed must be pre-erased. 2 Erase page. A 512-byte page of Flash memory address is erased. The page is selected by the address in EADRH/L. Any address in the page can be written to EADRH/EADRL to select it for erasure. 3 Erase all. All 62 kB of the available Flash memory are erased. Note that this command is used during serial mode and parallel download mode but should not be executed by user code. 4 Read byte. The byte in the Flash memory, addressed by EADRH/L, is read into EDATA. 5 Reserved. 6 Reserved. 7 Reserved. 8 Protect code (see the Protecting the Flash Memory section).
Table 96. Flash Key SFR (FLSHKY, 0xBA)
Bit 7 to 0 Mnemonic FLSHKY Default 0xFF Description The content of this SFR is compared to the Flash key, 0x3B. If the two values match the next ECON operation is allowed (see the Protecting the Flash Memory section).
Table 97. Flash Protection Key SFR (PROTKY, 0xBB)
Bit 7 to 0 Mnemonic PROTKY Default 0xFF Description The content of this SFR is compared to the flash memory location at Address 0xF7EA. If the two values match, the update of the write/erase and read protection set up is allowed (see the Protecting the Flash Memory section). If the protection key in the flash is 0xFF, the PROTKY SFR value is not used for comparison. The PROTKY SFR is also used to write the protection key in the flash. This is done by writing the desired value in PROTKY and writing 0x08 in the ECON SFR. This operation can only be done once.
Table 98. Flash Data SFR (EDATA, 0xBC)
Bit 7 to 0 Mnemonic EDATA Default 0 Description Flash pointer data.
Table 99. Flash Low Byte Address SFR (EADRL, 0xC6)
Bit 7 to 0 Mnemonic EADRL Default 0 Description Flash pointer low byte address.
Table 100. Flash High Byte Address SFR (EADRH, 0xC7)
Bit 7 to 0 Mnemonic EADRH Default 0 Description Flash pointer high byte address.
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Preliminary Technical Data
Flash Functions
The following sample 8051 code is provided below to demonstrate how to use the Flash functions. For these examples, the byte of flash memory, 0x3C00 is accessed.
ADE5166/ADE5169/ADE5566/ADE5569
Address 0xF7FF (see Figure 74). 16 bytes are reserved for write/erase protection, 4 bytes for read protection and another byte to set the protection security key. The user must enable write/erase protection for the last page at a minimum for the entire protection scheme to work. Note that the read protection does not prevent MOVC commands from being executed within the code. There is an additional layer of protection offered by a protection security key. The user can setup a protection security key so that the protection scheme cannot be changed without this key. Once the protection key has been configured, it may not be modified.
Write Byte
Write 0xF3 into Flash Memory Byte 0x3C00.
MOV EDATA, #F3h MOV EADRH, #3Ch MOV EADRL, #00h MOV FLSHKY, #3Bh key. MOV ECON, #01H ; Write Flash security ; Write Byte ; Data to be written ; Set up byte address
Enabling Flash Protection by Code
The protection bytes in the Flash can be programmed using Flash controller command and programming ECON to 0x08. Issuing the ECON protection command initiates the programming of 1 byte of protection data. The EADRL and EDATA data pointers are used to store the least significant address and data bytes, respectively. Note that the EADRH data pointer is not used in this command. The following sequence should be followed to enable the flash protection: 1. Set the EDATA data pointer with the write/erase or read protection data. When erased, the protection bits default to 1, like any other bit of flash memory. The default protection setting is for no protection. To enable protection, write a 0 to the bits corresponding to the pages that should be protected. Note that when setting the read protection that each protection bit protects four pages. Set the EADRL data pointer with the least significant byte of the protection address. For example, to access the protection on the Page 112 through Page 119 (Address 0xF7FE), EADRL should be written to 0xFE. Enable access to the flash by writing 3Bh to the FLSHKY register. Issue the protection command by writing 08H to the ECON register.
Erase Page
Erase the page containing flash memory byte 0x3C00.
MOV EADRH, #3Ch byte address MOV EADRL, #00h MOV FLSHKY, #3Bh key. MOV ECON, #02H ; Write Flash security ; Erase Page ; Select page through
Erase All
Erase all of the 62 kB flash memory.
MOV FLSHKY, #3Bh key. MOV ECON, #03H ; Write Flash security ; Erase All
Read Byte
Read Flash Memory Byte 0x3C00.
MOV EADRH, #3Ch MOV EADRL, #00h MOV FLSHKY, #3Bh key. MOV ECON, #04H ; Write Flash security ; Setup byte address
2.
3.
; Read Byte
; Data is ready in EDATA register
4.
Note that the read byte command can be used to view the status of the protection bytes located in the upper 21 bytes, Page 123. The write byte command is not valid for this area.
PROTECTING THE FLASH MEMORY
Two forms of protection are offered for this flash memory: read protection and write/erase protection. The read protection ensures that any pages that are read protected cannot be read by the end user. The write protection ensures that the flash memory cannot be erased or written over. This protects the end system from tampering and can prevent the code from being overwritten in the event of a runaway program. Write/erase protection is individually selectable for all 124 pages. Read protection is selected in groups of four pages (see Figure 73 for the groupings). The protection bits are stored in the last flash memory locations, Address 0xF7EB through
Step 1 to Step 3 should be repeated for each byte that requires protection. While configuring the final byte of write/read protection, the PROTKY can be enabled for a further level of code security. If enabled, the protection key is required to modify the protection scheme. To enable the protection key, the flash location 0xF7EB where the PROTKY is located should be written to using the ECON protection command (0x8). The PROTKY can be written to any 8-bit value, but once configured, it cannot be modified. To enable the PROTKY and activate the flash protection, the part has to be reset. Note that once the PROTKY has been activated by a reset any further changes to the protection require the new 8-bit protection key to be written to the PROTKY SFR prior to issuing the ECON command. The PROTKY SFR is cleared automatically when the ECON 0x8 command is issued and, therefore, the user must
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ensure that the correct value is written to the PROTKY SFR each time the protection scheme is changed. The two most significant bits of 0xF7FF are used to enable the lock mechanisms for the watchdog and stack boundary settings (see the Watchdog Timer section and the Stack Boundary Protection section for more information). The following code provides an example of how the write/erase protection can be enabled on the first page and the PROTKY set to 0xA3. Note that to active the following protection, the part requires a reset.
; enable write/erase protection on the first page only MOV EDATA, #0FEH MOV EADRL, #0F0H MOV FLSHKY, #3BH MOV ECON, #08H command ; clear bit WP 0 ; write address to F7F0h ; enable flash access ;issue protection
Preliminary Technical Data
;enable write/erase protection on last page (this is required for any protection to be activated) MOV EDATA, #0F7H MOV EADRL, #0FFH MOV FLSHKY, #3BH MOV ECON, #08H command MOV EDATA, #0A3H MOV EADRL, #0EBH MOV FLSHKY, #3BH MOV ECON, #08H command ; clear bit WP123 ; write address to F7FFh ; enable flash access ;issue protection
;set up PROTKY to A3h ; set PROTKY to A3h ; write address to F7EBh ; enable flash access ; issue protection
Note that once PROTKY is changed to 0xA3, as shown in the preceding example code, all future modifications of the protection scheme require the PROTKY SFR to be set to 0xA3 prior to issuing the ECON protection command.
WP 123 WP 117 WP 109 WP 116 WP 108 WP 115 WP 107 WP 122 WP 114 WP 106 WP 121 WP 113 WP 105 WP 120 WP 112 WP 104
0xF7FF WDOG LOCK WP 119 WP 111 STCON LOCK WP 118 WP 110
WP 15 WP 7 0xF7EF
WP 14 WP 6 RP
WP 13 WP 5 RP
WP 12 WP 4 RP
WP 11 WP 3 RP
WP 10 WP 2 RP
WP 9 WP 1 RP
WP 8 WP 0 RP
120 TO 123 116 TO 119 112 TO 115 108 TO 111 104 TO 107 100 TO 103 96 TO 99
RP RP RP RP RP RP RP RP 92 TO 95 88 TO 91 84 TO 87 80 TO 83 76 TO 79 72 TO 75 68 TO 71 64 TO 67 RP RP RP RP RP RP RP RP 60 TO 63 56 TO 59 52 TO 55 48 TO 51 44 TO 47 40 TO 43 36 TO 39 32 TO 35 RP RP RP RP RP RP 28 TO 31 24 TO 27 20 TO 23 16 TO 19 12 TO 15 8 TO 11 RP 4 TO 7 RP 0 TO 3
PROTECTION KEY
PROTKY 0xF7EB
0xF600
Figure 74. Flash Protection in Page124
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Preliminary Technical Data
Enabling Flash Protection by Emulator Commands
Another way to set the Flash protection bytes is to use the reserved emulator commands available only in download mode. These commands write directly to the SFRs and can be used to duplicate the operation mentioned in the Enabling Flash Protection by Code section. Once these Flash bytes are written, the part can exit emulation mode by reset and the protections will be effective. This method can be used in production and implemented after downloading the program. The commands used for this operation are an extension of the commands listed in Application Note uC004, Understanding the Serial Download Protocol, available at www.analog.com. * * Command with ASCII code I or 0x49 write the data into R0. Command with ASCII code F or 0x46 write R0 into the SFR address defined in the data of this command.
ADE5166/ADE5169/ADE5566/ADE5569
Flash Memory Timing
Typical program and erase times for the flash memory are shown in Table 101.
Table 101. Flash Memory Program and Erase Times
Command Write Byte Erase Page Erase All Read Byte Bytes Affected 1 byte 512 bytes 62 kB 1 bytes Flash Memory Timing 30 us 20 ms 2.5 sec 100 ns
Omitting the protocol defined in uC004, the sequence to load protections is similar to the sequence mentioned in the Enabling Flash Protection by Code section, except that two emulator commands are necessary to replace one assembly command. For example, to write the protection value in EADRH, the two following commands need to be executed: * * Command I with Data = value of Protection Byte 0x3FFF Command F with Data = 0xC7
Note that the core microcontroller operation is idled until the requested flash memory operation is complete. In practice, this means that even though the Flash operation is typically initiated with a two-machine-cycle MOV instruction (to write to the flash control SFR (ECON, 0xB9), the next instruction is not executed until the Flash/EE operation is complete. This means that the core cannot respond to interrupt requests until the Flash/EE operation is complete, although the core peripheral functions such as counter/timers continue to count as configured throughout this period.
IN CIRCUIT PROGRAMMING
Serial Downloading
The ADE5166/ADE5169/ADE5566/ADE5569 facilitate code download via the standard UART serial port. The parts enter serial download mode after a reset or a power cycle if the SDEN pin is pulled low through an external 1 k resistor. Once in serial download mode, the hidden embedded download kernel executes. This allows the user to download code to the full 62 kB of flash memory while the device is in circuit in its target application hardware. Protection configured in the last page of the ADE5166/ADE5169/ ADE5566/ADE5569 affects whether flash memory can be accessed in serial download mode. Read protected pages cannot be read. Write/erase protected pages cannot be written or erased. The configuration bits cannot be programmed in serial download mode.
Following this protocol, the protection can be written to the Flash using the same sequence as mentioned in the Enabling Flash Protection by Code paragraph. When the part is reset the protection will be effective.
Notes on Flash Protection
The flash protection scheme is disabled by default so that none of the pages of the flash are protected from reading or writing/ erasing. The last page must be write-/erase-protected for the protection scheme to work. To activate the protection settings, the ADE5166/ADE5169/ ADE5566/ADE5569 must be reset after configuring the protection. After configuring protection on the last page and resetting the part, protections that have been enabled can only be removed by mass erasing the flash memory. The protection bits are never truly write protected. Protection bits can be programmed modified from a 1 to a 0, even after the last page has been protected. In this way, more protection can be added but none can be removed. When the last page is read protected, the protection bits can still be read by the user code. All other bits on this page are not available for reading. The protection scheme is intended to protect the end system. Protection should be disabled while developing and emulating code.
Rev. PrB | Page 105 of 148
ADE5166/ADE5169/ADE5566/ADE5569 TIMERS
Each ADE5166/ADE5169/ADE5566/ADE5569 has three 16-bit timer/counters: Timer/Counter 0, Timer/Counter 1, and Timer/ Counter 2. The timer/counter hardware is included on-chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx (x = 0, 1, or 2). All three timers can be configured to operate as timers or as event counters. When functioning as a timer, the TLx register is incremented every machine cycle. Thus, users can think of it as counting machine cycles. Because a machine cycle on a single cycle core consists of one core clock period, the maximum count rate is the core clock frequency.
Table 102. Timer SFRs
SFR TCON TMOD TL0 TL1 TH0 TH1 T2CON RCAP2L RCAP2H TL2 TH2 Address 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0xC8 0xCA 0xCB 0xCC 0xCD Bit Addressable Yes No No No No No Yes No No No No
Preliminary Technical Data
When functioning as a counter, the TLx register is incremented by a 1-to-0 transition at its corresponding external input pin: T0, T1, or T2. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. Because it takes two machine cycles (two core clock periods) to recognize a 1-to-0 transition, the maximum count rate is half the core clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. User configuration and control of all timer operating modes is achieved via the SFRs in Table 102.
Description Timer/Counter 0 and Timer/Counter 1 control (see Table 104). Timer/Counter 0 and Timer/Counter 1 mode (see Table 103). Timer 0 low byte (see Table 107). Timer 1 low byte (see Table 109). Timer 0 high byte (see Table 106). Timer 1 high byte (see Table 108). Timer/Counter 2 control (see Table 105). Timer 2 reload/capture low byte (see Table 113). Timer 2 reload/capture high byte (see Table 112). Timer 2 low byte (Table 111). Timer 2 high byte (see Table 110).
TIMER REGISTERS
Table 103. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, 0x89)
Bit 7 6 5 to 4 Mnemonic Gate1 C/T1 T1/M1, T1/M0 Default 0 0 00 Description Timer 1 gating control. Set by software to enable Timer/Counter 1 only when the INT1 pin is high and the TR1 control bit is set. Cleared by software to enable Timer 1 whenever the TR1 control bit is set. Timer 1 timer or counter select bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select the timer operation (input from internal system clock). Timer 1 mode select bits. T1/M[1:0] Result 00 TH1 operates as an 8-bit timer/counter. TL1 serves as a 5-bit prescaler. 01 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 10 8-Bit Autoreload Timer/Counter. TH1 holds a value to reload into TL1 each time it overflows. 11 Timer/Counter 1 Stopped. Timer 0 gating control. Set by software to enable Timer/Counter 0 only when the INT0 pin is high and the TR0 control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set. Timer 0 timer or counter select bit. Set by software to the select counter operation (input from T0 pin). Cleared by software to the select timer operation (input from internal system clock). Timer 0 mode select bits. T0/M[1:0] Result 00 TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler. 01 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler. 10 8-Bit Autoreload Timer/Counter. TH0 holds a value to reload into TL0 each time it overflows. 11 TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
Rev. PrB | Page 106 of 148
3 2 1 to 0
Gate0 C/T0 T0/M1, T0/M0
0 0 00
Preliminary Technical Data
Bit 7 6 5 4 3 Address 0x8F 0x8E 0x8D 0x8C 0x8B Mnemonic TF1 TR1 TF0 TR0 IE11 Default 0 0 0 0 0
ADE5166/ADE5169/ADE5566/ADE5569
Table 104. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, 0x88)
Description Timer 1 overflow flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the program counter (PC) vectors to the interrupt service routine. Timer 1 run control bit. Set by the user to turn on Timer/Counter 1. Cleared by the user to turn off Timer/Counter 1. Timer 0 overflow flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine. Timer 0 run control bit. Set by the user to turn on Timer/Counter 0. Cleared by the user to turn off Timer/Counter 0. External Interrupt 1 (INT1) flag. Set by hardware by a falling edge or by a zero level applied to the external interrupt pin, INT1, depending on the state of Bit IT1. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition activated. If level activated, the external requesting source controls the request flag rather than the on-chip hardware. External Interrupt 1 (IE1) trigger type. Set by software to specify edge sensitive detection, that is, 1to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level. External Interrupt 0 (INT0) flag. Set by hardware by a falling edge or by a zero level being applied to the external interrupt pin, INT0, depending on the state of Bit IT0. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition activated. If level activated, the external requesting source controls the request flag rather than the on-chip hardware. External Interrupt 0 (IE0) trigger type. Set by software to specify edge sensitive detection, that is, 1-to-0 transition. Cleared by software to specify level sensitive detection, that is, zero level.
2 1
0x8A 0x89
IT11 IE01
0 0
0
1
0x88
IT01
0
These bits are not used to control Timer/Counter 0 and Timer/Counter 1 but are instead used to control and monitor the external INT0 and INT1 interrupt pins.
Table 105. Timer/Counter 2 Control SFR (T2CON, 0xC8)
Bit 7 6 5 Address 0xCF 0xCE 0xCD Mnemonic TF2 EXF2 RCLK Default 0 0 0 Description Timer 2 overflow flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1. Cleared by user software. Timer 2 external flag. Set by hardware when either a capture or reload is caused by a negative transition on the T2EX pin and EXEN2 = 1. Cleared by user software. Receive clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its receive clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable Timer 1 overflow to be used for the receive clock. Transmit clock enable bit. Set by the user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in Serial Port Mode 1 and Serial Port Mode 3. Cleared by the user to enable Timer 1 overflow to be used for the transmit clock. Timer 2 external enable flag. Set by the user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by the user for Timer 2 to ignore events at T2EX. Timer 2 start/stop control bit. Set by the user to start Timer 2. Cleared by the user to stop Timer 2. Timer 2 timer or counter function select bit. Set by the user to select the counter function (input from the external T2 pin). Cleared by the user to select the timer function (input from on-chip core clock). Timer 2 capture/reload select bit. Set by the user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by the user to enable autoreloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow.
4
0xCC
TCLK
0
3
0xCB
EXEN2
0
2 1
0xCA 0xC9
TR2 C/T2
0 0
0
0xC8
CAP2
0
Rev. PrB | Page 107 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Table 106. Timer 0 High Byte SFR (TH0, 0x8C)
Bit 7 to 0 Mnemonic TH0 Default 0 Description Timer 0 Data High Byte.
Preliminary Technical Data
Mode 0 (13-Bit Timer/Counter)
Mode 0 configures an 8-bit timer/counter. Figure 75 shows Mode 0 operation. Note that the divide-by-12 prescaler is not present on the single cycle core.
fCORE
C/T0 = 0 TL0 TH0 (5 BITS) (8 BITS) INTERRUPT TF0
Table 107. Timer 0 Low Byte SFR (TL0, 0x8A)
Bit 7 to 0 Mnemonic TL0 Default 0 Description Timer 0 Data Low Byte.
Table 108. Timer 1 High Byte SFR (TH1, 0x8D)
Bit 7 to 0 Mnemonic TH1 Default 0 Description Timer 1 Data High Byte.
P0.6/T0
C/T0 = 1
TR0
CONTROL
Bit 7 to 0
Mnemonic TL1
Default 0
Description Timer 1 Data Low Byte.
GATE INT0
Figure 75. Timer/Counter 0, Mode 0
Table 110. Timer 2 High Byte SFR (TH2, 0xCD)
Bit 7 to 0 Mnemonic TH2 Default 0 Description Timer 2 Data High Byte.
Table 111. Timer 2 Low Byte SFR (TL2, 0xCC)
Bit 7 to 0 Mnemonic TL2 Default 0 Description Timer 2 Data Low Byte.
Table 112. Timer 2 Reload/Capture High Byte SFR (RCAP2H, 0xCB)
Bit 7 to 0 Mnemonic TH2 Default 0 Description Timer 2 Reload/ Capture High Byte.
Table 113. Timer 2 Reload/Capture Low Byte SFR (RCAP2L, 0xCA)
Bit 7 to 0 Mnemonic TL2 Default 0 Description Timer 2 Reload/ Capture Low Byte.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag, TF0. TF0 can then be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate0 = 0 or INT0 = 1. Setting Gate0 = 1 allows the timer to be controlled by the external input INT0 to facilitate pulse width measurements. TR0 is a control bit in the Timer/Counter 0 and Timer/Counter 1 control SFR (TCON, 0x88); the Gate0/Gate1 bits are in Timer/Counter 0 and Timer/Counter 1 mode SFR (TMOD, 0x89). The 13-bit register consists of all eight bits of Timer 0 high byte SFR (TH0, 0x8C) and the lower five bits of Timer 0 low byte SFR (TL0, 0x8A). The upper three bits of TL0 SFR are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer register runs with all 16 bits. Mode 1 is shown in Figure 76.
fCORE
C/T0 = 0 TL0 TH0 (8 BITS) (8 BITS) C/T0 = 1 P0.6/T0 TR0 CONTROL TF0 INTERRUPT
TIMER 0 AND TIMER 1
Timer/Counter 0 and Timer/Counter 1 Data Registers
Each timer consists of two 8-bit registers. They are Timer 0 high byte SFR (TH0, 0x8C), Timer 0 low byte SFR (TL0, 0x8A), Timer 1 high byte SFR (TH1, 0x8D), and Timer 1 low byte SFR (TL1, 0x8B) These can be used as independent registers or combined into a single 16-bit register, depending on the timer mode configuration (see Table 106 to Table 109).
GATE INT0
Timer/Counter 0 and Timer/Counter 1 Operating Modes
This section describes the operating modes for Timer/Counter 0 and Timer/Counter 1. Unless otherwise noted, these modes of operation are the same for both Timer 0 and Timer 1.
Figure 76. Timer/Counter 0, Mode 1
Rev. PrB | Page 108 of 148
07411-072
07411-071
Table 109. Timer 1 Low Byte SFR (TL1, 0x8B)
Preliminary Technical Data
Mode 2 (8-Bit Timer/Counter with Autoreload)
Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload as shown in Figure 77. Overflow from TL0 not only sets TF0 but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged.
fCORE
C/T0 = 0 TL0 (8 BITS) INTERRUPT
ADE5166/ADE5169/ADE5566/ADE5569
TIMER 2
Timer/Counter 2 Data Registers
Timer/Counter 2 also has two pairs of 8-bit data registers associated with it: Timer 2 high byte SFR (TH2, 0xCD), Timer 2 low byte SFR (TL2, 0xCC), Timer 2 reload/capture high byte SFR (RCAP2H, 0xCB), and Timer 2 reload/capture low byte SFR (RCAP2L, 0xCA). These are used as both timer data registers and as timer capture/reload registers (see Table 110 to Table 113).
TF0
C/T0 = 1 P0.6/T0 TRO RELOAD TH0 (8 BITS) CONTROL
Timer/Counter 2 Operating Modes
The following sections describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the Timer/Counter 2 control SFR (T2CON, 0xC8), as shown in Table 105 and Table 114.
Table 114. T2CON Operating Modes
RCLK or TCLK 0 0 1 X CAP2 0 1 X X TR2 1 1 1 0 Mode 16-bit autoreload 16-bit capture Baud rate Off
GATE INT0
Figure 77. Timer/Counter 0, Mode 2
Mode 3 (Two 8-Bit Timer/Counters)
Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. This configuration is shown in Figure 78. TL0 uses the Timer 0 control bits, C/T0, Gate0 (see Table 103), TR0, TF0 (see Table 104), and INT0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Therefore, TH0 controls the Timer 1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or it can be used by the serial interface as a baud rate generator. In fact, Timer1 can be used in any application not requiring an interrupt from Timer 1 itself.
fCORE
C/T0 = 0 TL0 (8 BITS) C/T0 = 1 TF0 CORE CLK/12 INTERRUPT
07411-073
16-Bit Autoreload Mode
Autoreload mode has two options that are selected by Bit EXEN2 in Timer/Counter 2 control SFR (T2CON, 0xC8). If EXEN2 = 0 when Timer 2 rolls over, it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16-bit value in both the Timer 2 reload/capture high byte SFR (RCAP2H, 0xCB) and Timer 2 reload/capture low byte SFR (RCAP2L, 0xCA) registers, which are preset by software. If EXEN2 = 1, Timer 2 performs the same events as when EXEN2 = 0 but adds a 1-to-0 transition at the external input T2EX, which triggers the 16-bit reload and sets EXF2. Autoreload mode is shown in Figure 79.
16-Bit Capture Mode
Capture mode has two options that are selected by Bit EXEN2 in Timer/Counter 2 control SFR (T2CON, 0xC8). If EXEN2 = 0, Timer 2 is a 16-bit timer or counter that, upon overflowing, sets Bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same events as when EXEN2 = 0 but adds a l-to-0 transition on the external input T2E, which causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into the RCAP2L and RCAP2H registers, respectively. In addition, the transition at T2EX causes Bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. Capture mode is shown in Figure 80. The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1. In either case, if Timer 2 is used to generate the baud rate, the TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts do not occur and do not have to be disabled. In this mode, the EXF2 flag can, however, still cause interrupts that can be used as a third external interrupt. Baud rate generation is described as part of the UART serial port operation in the UART Serial Interface section.
P0.6/T0
CONTROL TR0
GATE INT0
fCORE/12
TR1
TH0 (8 BITS)
INTERRUPT TF1
07411-074
Figure 78. Timer/Counter 0, Mode 3
Rev. PrB | Page 109 of 148
ADE5166/ADE5169/ADE5566/ADE5569
fCORE
C/ T2 = 0
Preliminary Technical Data
TL2 (8 BITS) TH2 (8 BITS)
P1.4/T2
C/ T2 = 1
CONTROL TR2 RELOAD TRANSITION DETECTOR RCAP2L RCAP2H TF2 TIMER INTERRUPT EXF2
P1.3/ T2EX
CONTROL EXEN2
07411-075
Figure 79. Timer/Counter 2, 16-Bit Autoreload Mode
fCORE
C/ T2 = 0 TL2 (8 BITS) TH2 (8 BITS) TF2
P1.4/T2
C/ T2 = 1
CONTROL TR2 CAPTURE
TRANSITION DETECTOR RCAP2L RCAP2H
TIMER INTERRUPT
P1.3/ T2EX CONTROL EXEN2
EXF2
Figure 80. Timer/Counter 2, 16-Bit Capture Mode
Rev. PrB | Page 110 of 148
07411-076
Preliminary Technical Data PLL
The ADE5166/ADE5169/ADE5566/ADE5569 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power savings when maximum core performance is not required. The default core clock is the PLL clock divided by 4, or 1.024 MHz. The ADE energy measurement clock is derived from the PLL clock and is maintained at 4.096 MHz/5 MHz (or 819.2 kHz) across all CD settings.
ADE5166/ADE5169/ADE5566/ADE5569
The PLL is controlled by the CD[2:0] bits in the power control SFR (POWCON, 0xC5). To protect erroneous changes to the POWCON SFR, a key is required to modify the register. First, the key SFR (KYREG, 0xC1) is written with the key, 0xA7, and then a new value is written to the POWCON SFR. If the PLL loses lock, the MCU is reset and the PLL_FLT bit is set in the peripheral configuration SFR (PERIPH, 0xF4). Set the PLL_FTL_ACK bit in the start ADC measurement SFR (ADCGO, 0xD8) to acknowledge the PLL fault, clearing the PLL_FLT bit.
PLL REGISTERS
Table 115. Power Control SFR (POWCON, 0xC5)
Bit 7 6 5 4 3 2 to 0 Mnemonic Reserved METER_OFF Reserved COREOFF Reserved CD[2:0] Default 1 0 0 0 010 Description Reserved. Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering functions are not needed in PSM0. This bit should be kept at 0 for proper operation. Set this bit to shut down the core if in the PSM1 operating mode. Reserved. Controls the core clock frequency (fCORE). fCORE = 4.096 MHz/2CD. CD[2:0] Result (fCORE in MHz) 000 4.096 001 2.048 010 1.024 011 0.512 100 0.256 101 0.128 110 0.064 111 0.032
Writing to the Power Control SFR (POWCON, 0xC5)
Note that writing data to the POWCON SFR involves writing 0xA7 into the key SFR (KYREG, 0xC1), followed by a write to the POWCON SFR.
Table 116. Key SFR (KYREG, 0xC1)
Bit 7 to 0 Mnemonic KYREG Default 0 Description Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it. Write 0xEA to the KYREG SFR before writing to the INTPR, HTHSEC, SEC, MIN, or HOUR timekeeping registers to unlock it.
Table 117. Start ADC Measurement SFR (ADCGO, 0xD8)
Bit 7 6 to 3 2 1 0 Address 0xDF 0xDE to 0xDB 0xDA 0xD9 0xD8 Mnemonic PLL_FTL_ACK Reserved VDCIN_ADC_GO TEMP_ADC_GO BATT_ADC_GO Default 0 0 0 0 0 Description Set this bit to clear the PLL fault bit, PLL_FLT in the PERIPH register. A PLL fault is generated if a reset was caused because the PLL lost lock. Reserved. Set this bit to initiate an external voltage measurement. This bit is cleared when the measurement request is received by the ADC. Set this bit to initiate a temperature measurement. This bit is cleared when the measurement request is received by the ADC. Set this bit to initiate a battery measurement. This bit is cleared when the measurement request is received by the ADC.
Rev. PrB | Page 111 of 148
ADE5166/ADE5169/ADE5566/ADE5569 RTC--REAL-TIME CLOCK
The ADE5166/ADE5169/ADE5566/ADE5569 have an embedded real-time clock (RTC); see Figure 81. The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the nominal crystal frequency and for variations in the external crystal frequency over temperature. By default, the RTC is active in all the power saving modes. The RTC counters retain their values through watchdog resets and external resets and are only reset during a power on reset. The ADE5166/ADE5169/ADE5566/ADE5569 provide two ways to access the RTC data: direct access through SFRs for configuration and indirect access through address and data SFR registers for the timekeeping registers and some other configuration. The address and data registers act as pointers to the RTC internal registers.
MOV CALL ... UpdateRTC: MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV RET
Preliminary Technical Data
RTCKey, #0EAh UpdateRTC
KYREG, RTCKey RTCDAT, #30 RTCPTR, #82h KYREG, RTCKey RTCDAT, #05 RTCPTR, #83h KYREG, RTCKey RTCDAT, #04 RTCPTR, #84h RTCKey, #00h
ACCESS TO RTC SFR
Access to the RTC SFRs is achieved by reading or writing to the SFR addresses detailed in the Access to Internal RTC Registers section. Writing to the indirect registers is protected by a key, as explained in the following section, while reading is not protected.
Reading Internal Energy Measurement Registers
When Bit 7 of the RTCPTR SFR is cleared, the content of the internal RTC data register designated by the address in RTCPTR is transferred to the RTCDAT SFR. The RTC cannot be stopped to read the current time because stopping the RTC would introduce an error in its timekeeping. Therefore, the RTC is read on-the-fly and the counter registers must be checked for overflow. This can be accomplished through the following 8052 assembly code:
ReadAgain: MOV 0 MOV MOV MOV MOV MOV MOV MOV MOV MOV RTCPTR #01 R0, RTCDAT RTCPTR, #02 R1, RTCDAT RTCPTR, #03 R2, RTCDAT RTCPTR, #04 R3, RTCDAT RTCPTR, #01 A, RTCDAT ; 00h is R0 in ; Read HTHSEC ; Read HOUR ; Read MIN ; Read SEC ; Read HTHSEC using Bank
ACCESS TO INTERNAL RTC REGISTERS
Access to the internal RTC measurement registers is achieved by writing to the RTC pointer address SFR (RTCPTR, 0xA3). The RTCPTR register selects the RTC register to be accessed and determines if a read or a write is performed (see Table 121).
Writing to Internal RTC registers
The RTC circuitry runs off a 32.768 kHz clock. The timekeeping registers, HTHSEC, SEC, MIN, HOUR, DAY, DATE, MONTH, and YEAR are updated with a 32.768 kHz clock. However, the TIMECON, TIMECON2 and INTVAL registers are updated with a 128Hz clock. It takes up to two 128 Hz clock cycles from when the MCU writes the TIMECON, TIMECON2, or INTVAL register until it is successfully updated in the RTC. When Bit 7 of RTCPTR SFR is set, the content of the RTCDAT SFR is transferred to the internal RTC register designated by the address in the RTCPTR SFR. To protect the RTC timekeeping registers from runaway code, a key must be written to the KYREG register to obtain write access to any of the RTC indirect registers. The KYREG should be set to 0xEA to unlock the timekeeping registers and is reset to zero after a timekeeping register is written. The RTC registers can be written using the following 8052 assembly code:
CJNE A, 00h, ReadAgain Bank 0
Rev. PrB | Page 112 of 148
Preliminary Technical Data
XTALOS _ TEMPERATURE ADC + XTALG2 XTALG1 AUTOCOMPEN 32.768kHz CRYSTAL
ADE5166/ADE5169/ADE5566/ADE5569
(x)
2
TEMPCAL
RTCCOMP
COMPENSATION
CALIBRATION
ITS1 ITS0 CALIBRATED 32.768kHz
8-BIT PRESCALER
HUNDREDTHS COUNTER HTHSEC ALSEC_EN EQUAL? ALMIN_EN EQUAL? ALHR_EN EQUAL? ALDAY_EN EQUAL? ALDAT_EN EQUAL? ALARM SECOND ALSEC INTERVAL TIMEBASE SELECTION MUX
SECOND COUNTER SEC
ALARM MINUTE ALMIN
MINUTE COUNTER MIN
ALARM HOUR ALHOUR
HOUR COUNTER HOUR
ITEN
ALARM DAY ALDAY
DAY COUNTER DAY 8-BIT INTERVAL COUNTER INTVAL MONTH COUNTER MONTH
ALARM DATE ALDATE
DAY COUNTER DATE
EQUAL?
ALINT_EN
07411-123
YEAR COUNTER YEAR ALFLAG RTC INTERRUPT
Figure 81. RTC Implementation
RTC SFR REGISTER LIST
Table 118.
SFR TIMECON TIMECON2 RTCPTR RTCDAT KYREG RTCCOMP TEMPCAL Address 0xA1 0xA2 0xA3 0xA4 0xC1 0xF6 0xF7 Bit Addressable No No No No No No No Description RTC configuration (see Table 119) RTC Configuration 2 (see Table 120) RTC pointer address (see Table 121) RTC pointer data (see Table 122) Key (see Table 125) RTC nominal compensation (see Table 123) RTC temperature compensation (see Table 124)
Rev. PrB | Page 113 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Table 119. RTC Configuration SFR (TIMECON, 0xA1)
Bit 7 6 5 to 4 Mnemonic Reserved ALFLAG ITS[1:0] Default N/A 0 0
Preliminary Technical Data
3
SIT
0
2 1
ITFLAG ITEN
0 0
Description Reserved. Alarm flag. This bit is set when the RTC registers match the enabled alarm registers. It can be cleared by the user to indicate that the alarm has been serviced. INTVAL timebase select bits. ITS[1:0] Timebase 00 1/128 sec 01 Second 10 Minute 11 Hour Interval timer one-time alarm. SIT Result 0 The ALARM flag is set after INTVAL counts and then another interval count starts. 1 The ALARM flag is set after one time interval. Interval timer flag. This bit is set when the configured time interval has elapsed. It can be cleared by the user to indicate that the alarm event has been serviced. Interval timer enable. ITEN Result 0 The interval timer is disabled. The 8-bit interval timer counter is reset. 1 Set this bit to enable the interval timer.
0
Unused
N/A
Table 120. RTC Configuration 2 SFR (TIMECON2, 0xA2)
Bit 7 to 5 4 Mnemonic Reserved ALDAT_EN Default N/A 0 Description Reserved. Alarm date enable. When this bit is set, the data in the AL_DATE register is compared to the data in the RTC DATE register. If the two values match and any other enabled RTC alarms also match, the ALFLAG is set. If enabled, an RTC interrupt occurs. Alarm day enable. When this bit is set, the data in the AL_DAY register is compared to the data in the RTC DAY register. If the two values match and any other enabled RTC alarms also match, the ALFLAG is set. If enabled, an RTC interrupt occurs. Alarm hour enable. When this bit is set, the data in the AL_HOUR register is compared to the data in the RTC HOUR register. If the two values match and any other enabled RTC alarms also match, the ALFLAG is set. If enabled, an RTC interrupt occurs. Alarm minute enable. When set, the data in the AL_MIN register is compared to the data in the RTC MIN register. If the two values match and any other enabled RTC alarms also match, the ALFLAG is set. If enabled, an RTC interrupt occurs. Alarm second enable. When this bit is set, the data in the AL_SEC register is compared to the data in the RTC SEC register. If the two values match and any other enabled RTC alarms also match, the ALFLAG is set. If enabled, an RTC interrupt occurs.
3
ALDAY_EN
0
2
ALHR_EN
0
1
ALMIN_EN
0
0
ALSEC_EN
0
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Preliminary Technical Data
Table 121. RTC Pointer Address SFR (RTCPTR, 0xA3)
Bit 7 Mnemonic RTCW_RB Default 0
ADE5166/ADE5169/ADE5566/ADE5569
Description Read/write selection. RTCW_RB Results 0 The RTC register at the address is read into the RTCDAT SFR. 1 The data in the RTCDAT SFR is written in the RTC register at the address. This operation is completed only if the KEYREG SFR is set to 0xEA, the instruction before writing to the RTCDAT SFR. Reserved. Target address for read/write operation.
6 to 5 4 to 0
Reserved RTC_ADDRESS
N/A 0
Table 122. RTC Pointer Data SFR (RTCDAT, 0xA4)
Bit 7 to 0 Mnemonic RTC_DATA Default 0 Description Location of data for read/write RTC operation.
Table 123. RTC Nominal Compensation SFR (RTCCOMP, 0xF6)
Bit 7 to 0 Mnemonic RTCCOMP Default 0 Description The RTCCOMP SFR holds the nominal RTC compensation value at 25C. Note that this register is reset after a watchdog reset, an external reset or a power on reset (POR).
Table 124. RTC Temperature Compensation SFR (TEMPCAL, 0xF7)
Bit 7 to 0 Mnemonic TEMPCAL Default 0 Description The TEMPCAL SFR is adjusted based on the temperature read in the TEMPADC to calibrate the RTC over temperature. This allows the external crystal shift to be compensated over temperature. Note that this register is reset after a watchdog reset, an external reset or a power-on reset (POR).
Table 125. Key SFR (KYREG, 0xC1)
Bit 7 to 0 Mnemonic KYREG Default 0 Description To unlock the POWCON SFR and enable a write operation, 0xA7 should be written to KYREG. To unlock the HTHSEC, SEC, MIN or HOUR timekeeping registers or the RTCCAL, XTALOS, XTALG1 or XTALG2 registers and enable a write operation, 0xEA should be written to KYREG.
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RTC REGISTERS
Table 126. RTC Register List
Address RTCPTR[4:0] 0x00 0x01 Mnemonic Reserved HTHSEC R/W N/A R/W Length N/A 8 Signed/ Unsigned N/A U Default Value N/A 0
Preliminary Technical Data
0x02
SEC
R/W
8
U
0
0x03
MIN
R/W
8
U
0
0x04
HOUR
R/W
8
U
0
0x05 0x06
DAY DATE
R/W R/W
8 8
U U
0 1
0x07
MONTH
R/W
8
U
1
0x08 0x09
YEAR INTVAL
R/W R/W
8 8
U U
0 0
0x0A
AL_SEC
R/W
8
U
0
0x0B
AL_MIN
R/W
8
U
0
0x0C
AL_HOUR
R/W
8
U
0
0x0D
AL_DAY
R/W
8
U
0
0x0E
AL_DATE
R/W
8
U
0
0x0F 0x10
RTC_CAL XTALOS
R/W R/W
8 8
U U
0 0
Description Reserved. This counter updates every 1/128 second, referenced from the calibrated 32.768 kHz clock. It overflows from 127 to 00, incrementing the seconds counter, SEC. This counter updates every second, referenced from the calibrated 32.768 kHz clock. It overflows from 59 to 00, incrementing the minutes counter, MIN This counter updates every minute, referenced from the calibrated 32.768 kHz clock. It overflows from 59 to 00, incrementing the hours counter, HOUR This counter updates every Hour, referenced from the calibrated 32.768 kHz clock. It overflows from 23 to 00, incrementing the DAY and DATE counters. This counter updates every day, referenced from the calibrated 32.768 kHz clock. It overflows from 6 to 0 This counter updates every day, referenced from the calibrated 32.768 kHz clock. It overflows from 28/29/30 or 31 to 01, depending on the month, incrementing the month counter, MONTH. This counter starts at 1 and updates every month, referenced from the calibrated 32.768 kHz clock. It overflows from 12 to 01, incrementing the year counter, YEAR. This counter updates every year, referenced from the calibrated 32.768 kHz clock. The interval timer counts according to the timebase established in the ITS[1:0] bits of the RTC Configuration SFR (TIMECON, 0xA1). Once the number of counts is equal to INTVAL, the ITFLAG flag is set and a pending RTC interrupt is created if enabled. Note that the interval counter is 8-bits so it could count up to 255 sec, for example. Alarm second register. When this register matches the SEC register and the ALSEC_EN bit is set, the ALFLAG is issued if all other enabled alarms match their corresponding timekeeping register. If enabled, a pending RTC interrupt is generated. Alarm minute register. When this register matches the MIN register and the ALMIN_EN bit is set the ALFLAG is issued if all other enabled alarms match their corresponding timekeeping register. If enabled, a pending RTC interrupt is generated. Alarm hour register. When this register matches the HOUR register and the ALHR_EN bit is set, the ALFLAG is issued if all other enabled alarms match their corresponding timekeeping register. If enabled, a pending RTC interrupt is generated. Alarm day register. When this register matches the DAY register and the ALDAY_EN bit is set the ALFLAG is issued if all other enabled alarms match their corresponding timekeeping register. If enabled, a pending RTC interrupt is generated.. Alarm date register. When this register matches the DATE register and the AL_DAT_EN bit is set the ALFLAG is issued if all other enabled alarms match their corresponding timekeeping register. If enabled, a pending RTC interrupt is generated. Configuration of the RTC calibration output (see Table 127). Temperature offset for crystal temperature compensation
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Preliminary Technical Data
Address RTCPTR[4:0] 0x11 0x12 Mnemonic XTALG1 XTALG2 R/W R/W R/W Length 8 8 Signed/ Unsigned U U Default Value 0 0
ADE5166/ADE5169/ADE5566/ADE5569
Description Least significant byte of frequency coefficient for crystal temperature compensation (see Table 128). Most significant byte of frequency coefficient for crystal temperature compensation (see Table 129)
Table 127. RTC Calibration Configuration Register (RTC_CAL, 0x0F)
Bit 7 6 Mnemonic Reserved CAL_EN Default 0 0 Description This bit should be kept cleared for proper operation. RTC calibration enable output. CAL_EN Result 0 The RTC calibration output signal is disabled. 1 The RTC calibration output signal is enabled and present on the pins selected by the RTC_CAL[3:0] bits. RTC calibration output frequency selection. FSEL[1:0] Frequency Calibration window 00 1 Hz 30.5 seconds 01 512 Hz 30.5 seconds 10 500 Hz 0.244 second 11 16.384kHz 0.244 second When this bit is set and the CAL_EN bit is set, the RTC output is present on P2.3/SDEN/TxD2. When this bit is set and the CAL_EN bit is set, the RTC output is present on P1.2/FP25. When this bit is set and the CAL_EN bit is set, the RTC output is present on P0.7/SS/T1/RxD2. When this bit is set and the CAL_EN bit is set, the RTC output is present on P0.5/MISO/ZX.
5 to 4
FSEL[1:0]
0
3 2 1 0
RTC_P2P3 RTC_P1P2 RTC_P0P7 RTC_P0P5
0 0 0 0
Table 128. Crystal Gain Register MSB ( (XTALG2, 0x12)
Bit 7 6 to 0 Mnemonic AUTOCOMPEN XTALGain[6:0] Default 0 0 Description Automatic crystal temperature compensation enable. Setting this bit to one enables the automatic compensation. Upper seven bits of crystal temperature coefficient.
Table 129. Crystal Gain Register LSB (XTALG1, 0x11)
Bit 7 to 0 Mnemonic XTALGain[14:7] Default 0 Description Least significant byte of crystal temperature coefficient.
RTC CALENDAR
The RTC has a full calendar taking into account leap years. The rollover of the date to increment the month is implemented following Table 130.
Table 130. Month Rollover
MONTH Register 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C Rollover Value 31 28 or 29 days (see Table 131) 31 30 31 30 31 31 30 31 30 31 Estimated Month January February March April May June July August September October November December
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Table 131. Leap Years--Rollover After 29 Days
Year Register 0d04 0d08 0d12 0d16 0d20 0d24 0d28 0d32 0d36 0d40 0d44 0d48 0d52 0d56 0d60 0d64 0d68 0d72 0d76 0d80 0d84 0d88 0d96 0d96 Estimated Year 2004 2008 2012 2016 2020 2024 2028 2032 2036 2040 2044 2048 2052 2056 2060 2064 2068 2072 2076 2080 2084 2088 2092 2096
Preliminary Technical Data
Interval Timer Alarm
The RTC can be used as an interval timer. When the interval timer is enabled by setting the ITEN bit in the RTC configuration SFR (TIMECON, 0xA1), the interval timer clock source selected by the ITS1 and ITS0 bits is passed through to an 8-bit counter. This counter increments on every interval timer clock pulse until the 8-bit counter is equal to the value in the alarm interval register. Then an alarm event is generated, setting the SIT flag and creating a pending RTC interrupt. If the SIT bit in the RTC configuration SFR (TIMECON, 0xA1) is clear, the 8-bit counter is cleared and starts counting again. If the SIT bit is set then the 8-bit counter is held in reset after the alarm occurs. Take care when changing the interval timer timebase. The recommended procedure is as follows: 1. If the INTVAL register is going to be modified, write this register first. Then wait for one 128 Hz clock cycle to synchronize with the RTC, 64,000 cycles at a 4.096 MHz instruction cycle clock. Disable the interval timer by clearing the ITEN bit in the TIMECON SFR. Then wait for one 128 Hz clock cycle to synchronize with the RTC, 64,000 cycles at a 4.096 MHz instruction cycle clock. Read the TIMECON SFR to ensure that the ITEN bit is clear. If it is not, wait for another 128 Hz clock cycle. Set the timebase bits, ITS[1:0] in the TIMECON SFR to configure the interval. Wait for a 128 Hz clock cycle for this change to take effect.
2.
3. 4.
RTC INTERRUPTS
The RTC alarm and interval timer interrupts are enabled by setting the ETI bit in the interrupt enable and Priority 2 SFR (IEIP2, 0xA9). When an alarm or Interval Timer event occurs, the corresponding flag is set and a pending RTC interrupt is generated. If the RTC interrupt is enabled, the program vectors to the RTC interrupt address and the corresponding RTC flag can be cleared in software. Moving to the RTC interrupt address alone does not automatically clear the flag. To successfully acknowledge the interrupt event, the flag has to be cleared by software. If the RTC interrupt is disabled when the event occurs, the pending interrupt remains until the corresponding RTC flag is cleared. The ALFLAG and ITFLAG flags therefore drive the RTC interrupt, and should be managed by the user to keep track of the RTC events. Note that if the ADE5166/ADE5169/ADE5566/ADE5569 are awakened by an RTC event, either the ALFLAG or ITFLAG, then the pending RTC interrupt must be serviced before the ADE5166/ADE5169/ADE5566/ADE5569 can go back to sleep again. The ADE5166/ADE5169/ADE5566/ADE5569 keep waking up until this interrupt has been serviced.
Alarm
The RTC can be used with an alarm to wake up periodically. The alarm registers (AL_SEC, AL_MIN, AL_HOUR, AL_DAY, and AL_DATE) should be set to the specific time that the alarm event is required, and the corresponding Alxx_EN bits set in the TIMECON2 SFR (0xA2). The enabled alarm registers are then compared to their respective RTC registers (SEC, MIN, HOUR, DAY, and DATE) and when all enabled alarms match their corresponding RTC registers, the alarm flag is set and a pending interrupt is generated. The alarm flag is located in Bit 6 of the TIMECON2 SFR (0xA2). If enabled, an RTC interrupt occurs and the program vectors to the RTC interrupt address.
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Preliminary Technical Data
RTC CRYSTAL COMPENSATION
The RTC provides registers to compensate for the tolerance of the crystal frequency and its variation over temperature. Up to 248 ppm frequency error can be calibrated out by the RTC circuitry. The compensation is fully digital and implemented by adding or subtracting pulses from the crystal clock signal. The resolution of the RTC compensation register is 2 ppm/LSB, or 0.17 s/day/LSB. The RTC compensation circuitry adds the RTC temperature compensation SFR (TEMPCAL, 0xF7) and the RTC nominal compensation SFR (RTCCOMP, 0xF6) to determine how much compensation is required and the sum of these two registers is limited to 248ppm, or 42.85 s/day.
ADE5166/ADE5169/ADE5566/ADE5569
When no RTC compensation is applied, with RTCCOMP and TEMPCAL equal to zero, the nominal compensation required to account for the error in the external crystal can be determined. In this case, it is not necessary to wait for an entire calibration window to determine the error in the pulse output. Calculating at the error in frequency between two consecutive pulses on the RTC calibration pin is sufficient. The value to write to the RTCCOMP register is calculated from the % error or seconds per day error on the frequency output. Each LSB of the RTCCOMP SFR represents 2 ppm of correction where1 s/day error is equal to 11.57 ppm.
RTCCOMP = 5000 x (% Error)
RTCCOMP = 1 x (s / day Error ) 2 x 11.57
RTC Calibration
The nominal crystal frequency can be calibrated by adjusting the RTCCOMP register so that the clock going into the RTC is precisely 32.768 kHz at 25C.
Calibration Flow
An RTC calibration pulse output is on up to four pins configured by the four LSBs in the RTC calibration configuration register (RTC_CAL, 0x0F). Enable the RTC output by setting the CAL_EN bit in the RTC calibration configuration register (RTC_CAL, 0x0F). The RTC calibration is accurate to within 2 ppm over a 30.5 sec window in all operational modes: PSM0, PSM1, and PSM2. Two output frequencies are offered for the normal RTC mode: 1 Hz with FSEL[1:0] = 00 and 512Hz with FSEL[1:0] = 01 in the RTC calibration configuration register (RTC_CAL, 0x0F). A shorter window of 0.244 sec is offered for fast calibration during PSM0 or PSM1. Two output frequencies are offered for this RTC calibration output mode: 500 Hz with FSEL[1:0] = 10 and 16.384 kHz with FSEL[1:0] = 11 in the RTC calibration configuration register (RTC_CAL, 0x0F). Note that for the 0.244 sec calibration window, the RTC is clocked 125 times faster than in the normal mode, resulting in timekeeping registers that represent seconds/125, minutes/125, and hours/125 instead of seconds, minutes, and hours. Therefore, this mode should be used for calibration only.
Table 132. RTC Calibration Options
Option Normal Mode 0 Normal Mode 1 Calibration Mode 0 Calibration Mode 1 FSEL[1:0] 00 01 10 11 Calibration Window (sec) 30.5 30.5 0.244 0.244 fRTCCAL (Hz) 1 512 500 16384
During calibration, user software writes the RTC with the current time. Refer to the Access to Internal RTC Registers section for more information on how to read and write the RTC timekeeping registers.
RTC TEMPERATURE COMPENSATION
The RTC temperature compensation SFR (TEMPCAL, 0xF7) is used to compensate for the external crystal drift over temperature by adding or subtracting additional pulses based on temperature. By design, crystal frequency's changes with temperature according to Equation 35. XTAL frequency(T ) - XTAL frequency(T0 ) =
k x (T - T0 )2
(35)
where k and T0 are given by the crystal manufacturer. The ADE5166/ADE5169/ADE5566/ADE5569 provide the unique feature of using its internal temperature measurement to process the TEMPCAL register value based on the theoretical inverted parabolic curve described in Equation 35. The coefficient k and T0 are user programmable. The crystal manufacturer coefficients need to be translated to fit the format of crystal offset (XTALOS) and crystal gain (XTALGain), which is a combination of the XTALG1 and XTALG2 registers of the ADE5166/ADE5169/ADE5566/ ADE5569. The actual implementation of Equation 35 in the ADE5166/ADE5169/ADE5566/ADE5569 is as follows:
TEMPCAL[7 : 0] = XTALGain x 215
(TEMPADC[7 : 0] - XTALOS[7 : 0])2
where XTALGain = XTALG2[6:0] x 28 + XTALG1[7:0]
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Because the temperature measurement has a resolution of 0.78C/LSB and the RTC compensation has a resolution of 2ppm/LSB, XTALOS and XTALGain can be processed using
XTALOS[7:0] = TEMPADC[7:0]T0
Preliminary Technical Data
(STRBPER, 0xF9). Background measurements occur every 1, 2, or 8 minutes, depending on the configuration. When the MSB of XTALG2 is set and background temperature readings are initiated, the RTC calibration is performed every time a new temperature measurement is obtained. Note that the temperature and supply delta SFR (DIFFPROG, 0xF3) does not have to be set for the RTC temperature compensation to be operational. Note that because the RTC temperature compensation is designed to operate in the background, it does not affect the temperature, voltage or battery ADC SFRs. These registers are only updated when configured to do so in the temperature and supply delta SFR (DIFFPROG, 0xF3) in background mode, or upon the completion of a single ADC reading initiated by a write to the start ADC measurement SFR (ADCGO, 0xD8). All of the ADC measurements can therefore be used in parallel with the RTC temperature calibration. It should be noted, however, that the frequency of background temperature measurements is restricted by the strobe interval set in the peripheral ADC strobe period (STRBPER, 0xF9) when the RTC temperature compensation was configured.
considering the equation of the temperature ADC at 25C, XTALOS = 0d123, if T0 is given to be 25C.
XTALGain[14 : 0] = (- k x 2ppm / C x 0.78C/LSB)x 2 14
where: k is a negative number usually presented with the unit of ppm/C. XTALGain is an unsigned 15-bit number made up of Register XTALG1 and Register XTALG2. The automatic correction is disabled by default and can be enabled by writing 1 to the MS of the XTALG2 register. When enabled, TEMPCAL can be read but cannot be written by user code. To successfully perform the autocalibration, a temperature reading must first be obtained (see the Temperature Measurement section). This calibration feature is designed to operate in the background to continually maintain an accurate RTC value with changing temperature. It is therefore recommended that temperature measurements be set up to occur automatically in the background through the peripheral ADC strobe period SFR
Rev. PrB | Page 120 of 148
Preliminary Technical Data UART SERIAL INTERFACE
The ADE5166/ADE5169/ADE5566/ADE5569 UART can be configured in one of four modes.
* * * *
ADE5166/ADE5169/ADE5566/ADE5569
and TxD (P1.1) pins, and the firmware interface is through the SFRs presented in Table 133. Both the serial port receive and transmit registers are accessed through the serial port buffer SFR (SBUF, 0x99). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. An enhanced UART mode is offered by using the UART timer and by providing enhanced frame error, break error, and overwrite error detection. This mode is enabled by setting the EXTEN bit in the configuration SFR (CFG, 0xAF) (see the UART Additional Features section). The enhanced serial baud rate control SFR (SBAUDT, 0x9E) and UART timer fractional divider SFR (SBAUDF, 0x9D) are used to configure the UART timer and to indicate the enhanced UART errors.
Shift register with baud rate fixed at fCORE/12 8-bit UART with variable baud rate 9-bit UART with baud rate fixed at fCORE/64 or fCORE/32 9-bit UART with variable baud rate
Variable baud rates are defined by using an internal timer to generate any rate between 300 bauds/s and 115,200 bauds/s. The UART serial interface provided in the ADE5166/ADE5169/ ADE5566/ADE5569 is a full-duplex serial interface. It is also receive buffered by storing the first received byte in a receive buffer until the reception of the second byte is complete. The physical interface to the UART is provided via the RxD (P1.0)
UART REGISTERS
Table 133. Serial Port SFRs
SFR SCON SBUF SBAUDT SBAUDF Address 0x98 0x99 0x9E 0x9D Bit Addressable Yes No No No Description Serial communications control (see Table 134). Serial port buffer (see Table 135). Enhanced serial baud rate control (see Table 136). UART timer fractional divider (see Table 137).
Table 134. Serial Communications Control SFR (SCON, 0x98)
Bit 7 to 6 Address 0x9F, 0x9E Mnemonic SM0, SM1 Default 00 Description UART serial mode select bits. These bits select the serial port operating mode. SM[0:1] Result (Selected Operating Mode) 00 Mode 0, shift register, fixed baud rate (fCORE/12). 01 Mode 1, 8-bit UART, variable baud rate. 10 Mode 2, 9-bit UART, fixed baud rate (fCORE/32) or (fCORE/16). 11 Mode 3, 9-bit UART, variable baud rate. Multiprocessor communication enable bit. Enables multiprocessor communication in Mode 2 and Mode 3, and framing error detection in Mode 1. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as the byte of data is received. In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI is set as soon as the byte of data is received. Serial port receive enable bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. Serial port transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in Mode 2 and Mode 3. Serial port receiver (Bit 9). The ninth data bit received in Mode 2 and Mode 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8. Serial port transmit interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3. TI must be cleared by user software. Serial port receive interrupt flag. Set by hardware at the end of the eighth bit in Mode 0 or halfway through the stop bit in Mode 1, Mode 2, and Mode 3. RI must be cleared by user software.
5
0x9D
SM2
0
4 3 2 1
0x9C 0x9B 0x9A 0x99
REN TB8 RB8 TI
0 0 0 0
0
0x98
RI
0
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Table 135. Serial Port Buffer SFR (SBUF, 0x99)
Bit 7 to 0 Mnemonic SBUF Default 0
Preliminary Technical Data
Description Serial Port Data Buffer.
Table 136. Enhanced Serial Baud Rate Control SFR (SBAUDT, 0x9E)
Bit 7 Mnemonic OWE Default 0 Description Overwrite error. This bit is set when new data is received and RI = 1. It indicates that SBUF was not read before the next character was transferred in, causing the prior SBUF data to be lost. Write a 0 to this bit to clear it. Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read only and updated every time a frame is received. Break error. This bit is set whenever the receive data line (Rx) is low for longer than a full transmission frame, which is the time required for a start bit, eight data bits, a parity bit, and half a stop bit. This bit is updated every time a frame is received. Extended divider ratio for baud rate setting as shown in Table 138. Binary divider. See Table 138. DIV[2:0] Result 000 Divide by 1. 001 Divide by 2. 010 Divide by 4. 011 Divide by 8. 100 Divide by 16. 101 Divide by 32. 110 Divide by 64. 111 Divide by 128.
6 5
FE BE
0 0
4, 3 2, 1, 0
SBTH1, SBTH0 DIV2, DIV1, DIV0
0 0
Table 137. UART Timer Fractional Divider SFR (SBAUDF, 0x9D)
Bit 7 Mnemonic UARTBAUDEN Default 0 Description UART baud rate enable. Set to enable UART timer to generate the baud rate. When set, PCON.7 (SMOD), T2CON.4 (TCLK), and T2CON.5 (RCLK) are ignored. Cleared to let the baud rate be generated as per a standard 8052. Not Implemented, write don't care. UART Timer Fractional Divider Bit 5. UART Timer Fractional Divider Bit 4. UART Timer Fractional Divider Bit 3. UART Timer Fractional Divider Bit 2. UART Timer Fractional Divider Bit 1. UART Timer Fractional Divider Bit 0.
6 5 4 3 2 1 0
SBAUDF.5 SBAUDF.4 SBAUDF.3 SBAUDF.2 SBAUDF.1 SBAUDF.0
0 0 0 0 0 0
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Preliminary Technical Data
Ideal Baud 115,200 115,200 57,600 57,600 38,400 38,400 38,400 19,200 19,200 19,200 19,200 9600 9600 9600 9600 9600 4800 4800 4800 4800 4800 4800 2400 2400 2400 2400 2400 2400 2400 300 300 300 300 300 300 300 300 CD 0 1 0 1 0 1 2 0 1 2 3 0 1 2 3 4 0 1 2 3 4 5 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 SBTH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 DIV 1 0 2 1 2 1 0 3 2 1 0 4 3 2 1 0 5 4 3 2 1 0 6 5 4 3 2 1 0 7 7 7 6 5 4 3 2
ADE5166/ADE5169/ADE5566/ADE5569
SBAUDT 0x01 0x00 0x02 0x01 0x02 0x01 0x00 0x03 0x02 0x01 0x00 0x04 0x03 0x02 0x01 0x00 0x05 0x04 0x03 0x02 0x01 0x00 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x17 0x0F 0x07 0x06 0x05 0x04 0x03 0x02 SBAUDF 0x87 0x87 0x87 0x87 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB 0xAB % Error +0.16 +0.16 +0.16 +0.16 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31
Table 138. Common Baud Rates Using UART Timer with a 4.096 MHz PLL Clock
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ADE5166/ADE5169/ADE5566/ADE5569
UART OPERATION MODES
Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12)
Mode 0 is selected when the SM0 and SM1 bits in the serial communications control register SFR (SCON, 0x98) are cleared. In this shift register mode, serial data enters and exits through RxD. TxD outputs the shift clock. The baud rate is fixed at fCORE/12. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to the serial port buffer SFR (SBUF, 0x99). The data is shifted out of the RxD line. The eight bits are transmitted with the least significant bit (LSB) first. Reception is initiated when the receive enable bit (REN) is 1 and the receive interrupt bit (RI) is 0. When RI is cleared, the data is clocked into the RxD line, and the clock pulses are output from the TxD line as shown in Figure 82.
RxD (DATA OUT) TxD (SHIFT CLOCK) DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7
07411-078
Preliminary Technical Data
All of the following conditions must be met at the time the final shift pulse is generated to receive a character:
*
*
If the extended UART is disabled (EXTEN = 0 in the CFG SFR), RI must be 0 to receive a character. This ensures that the data in the SBUF SFR is not overwritten if the last received character has not been read. If frame error checking is enabled by setting SM2, the received stop bit must be set to receive a character. This ensures that every character received comes from a valid frame, with both a start bit and a stop bit.
If any of these conditions are not met, the received frame is irretrievably lost, and the receive interrupt flag (RI) is not set. If the received frame has met the previous criteria, the following events occur:
* * *
The eight bits in the receive shift register are latched into the SBUF SFR. The ninth bit (stop bit) is clocked into RB8 in the SCON SFR. The receiver interrupt flag (RI) is set.
Figure 82. 8-Bit Shift Register Mode
Mode 1 (8-Bit UART, Variable Baud Rate)
Mode 1 is selected by clearing SM0 and setting SM1. Each data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1). Therefore, each frame consists of 10 bits transmitted on TxD or received on RxD. The baud rate is set by a timer overflow rate. Timer 1 or Timer 2 can be used to generate baud rates, or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. There is also a dedicated timer for baud rate generation, the UART timer, which has a fractional divisor to precisely generate any baud rate (see the UART Timer Generated Baud Rates section). Transmission is initiated by a write to the serial port buffer SFR (SBUF, 0x99). Next, a stop bit (1) is loaded into the ninth bit position of the transmit shift register. The data is output bit-bybit until the stop bit appears on TxD and the transmit interrupt flag (TI) is automatically set, as shown in Figure 83.
START BIT TxD TI (SCON.1)
07411-079
Mode 2 (9-Bit UART with Baud Fixed at fCORE/64 or fCORE/32)
Mode 2 is selected by setting SM0 and clearing SM1. In this mode, the UART operates in 9-bit mode with a fixed baud rate. The baud rate is fixed at fCORE/64 by default, although setting the SMOD bit in the program control SFR (PCON, 0x87) doubles the frequency to fCORE/32. Eleven bits are transmitted or received: a start bit (0), eight data bits, a programmable ninth bit, and a stop bit (1). The ninth bit is most often used as a parity bit or as part of a multiprocessor communication protocol, although it can be used for anything, including a ninth data bit, if required. To use the ninth data bit as part of a communication protocol for a multiprocessor network such as RS-485, the ninth bit is set to indicate that the frame contains the address of the device with which the master wants to communicate. The devices on the network are always listening for a packet with the ninth bit set and are configured such that if the ninth bit is cleared, the frame is not valid, and a receive interrupt is not generated. If the ninth bit is set, all devices on the network receive the address and obtain a receive character interrupt. The devices examine the address and, if it matches one of the device's preprogrammed addresses, that device configures itself to listen to all incoming frames, even those with the ninth bit cleared. Because the master has initiated communication with that device, all the following packets with the ninth bit cleared are intended specifically for that addressed device until another packet with the ninth bit set is received. If the address does not match, the device continues to listen for address packets.
STOP BIT D0 D1 D2 D3 D4 D5 D6 D7
SET INTERRUPT (FOR EXAMPLE, READY FOR MORE DATA)
Figure 83. 8-Bit Variable Baud Rate
Reception is initiated when a 1-to-0 transition is detected on RxD. Assuming that a valid start bit is detected, character reception continues. The eight data bits are clocked into the serial port shift register.
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Preliminary Technical Data
To transmit, the eight data bits must be written into the serial port buffer SFR (SBUF, 0x99). The ninth bit must be written to TB8 in the serial communications control SFR (SCON, 0x98). When transmission is initiated, the eight data bits from SBUF are loaded into the transmit shift register (LSB first). The ninth data bit, held in TB8, is loaded into the ninth bit position of the transmit shift register. The transmission starts at the next valid baud rate clock. The transmit interrupt flag (TI) is set as soon as the transmission completes, when the stop bit appears on TxD. All of the following conditions must be met at the time the final shift pulse is generated to receive a character:
*
ADE5166/ADE5169/ADE5566/ADE5569
UART BAUD RATE GENERATION
Mode 0 Baud Rate Generation
The baud rate in Mode 0 is fixed.
f Mode 0 Baud Rate = CORE 12
Mode 2 Baud Rate Generation
The baud rate in Mode 2 depends on the value of the PCON[7] (SMOD) bit in the program control SFR (PCON, 0x87). If SMOD = 0, the baud rate is 1/32 of the core clock. If SMOD = 1, the baud rate is 1/16 of the core clock.
Mode 2 Baud Rate =
2 SMOD x fCORE 32
*
If the extended UART is disabled (EXTEN = 0 in the CFG SFR), RI must be 0 to receive a character. This ensures that the data in SBUF is not overwritten if the last received character has not been read. If multiprocessor communication is enabled by setting SM2, the received ninth bit must be set to receive a character. This ensures that only frames with the ninth bit set, frames that contain addresses, generate a receive interrupt.
Mode 1 and Mode 3 Baud Rate Generation
The baud rates in Mode 1 and Mode 3 are determined by the overflow rate of the timer generating the baud rate, that is, either Timer 1, Timer 2, or the dedicated baud rate generator, UART timer, which has an integer and fractional divisor.
If any of these conditions are not met, the received frame is irretrievably lost, and the receive interrupt flag (RI) is not set. Reception for Mode 2 is similar to that of Mode 1. The eight data bytes are input at RxD (LSB first) and loaded onto the receive shift register. If the received frame has met the previous criteria, the following events occur:
* * *
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates in Mode 1 and Mode 3 are determined by the Timer 1 overflow rate. The value of SMOD is as follows:
Mode 1 or Mode 3 Baud Rate =
2 SMOD x Timer 1 Overflow Rate 32
The eight bits in the receive shift register are latched into the SBUF SFR. The ninth data bit is latched into RB8 in the SCON SFR. The receiver interrupt flag (RI) is set.
Mode 3 (9-Bit UART with Variable Baud Rate)
Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8052 UART serial port operates in 9-bit mode with a variable baud rate. The baud rate is set by a timer overflow rate. Timer 1 or Timer 2 can be used to generate baud rates, or both timers can be used simultaneously where one generates the transmit rate and the other generates the receive rate. There is also a dedicated timer for baud rate generation, the UART timer, which has a fractional divisor to precisely generate any baud rate (see the UART Timer Generated Baud Rates section). The operation of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 when RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1.
The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter operation, and in any of its three running modes. In the most typical application, it is configured for timer operation in autoreload mode (high nibble of TMOD = 0010 binary). In that case, the baud rate is given by the following formula:
SMOD Mode 1 or Mode 3 Baud Rate = 2 x
32
f CORE ( 256 - TH1)
Timer 2 Generated Baud Rates
Baud rates can also be generated by using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted or received. Because Timer 2 has a 16-bit autoreload mode, a wider range of baud rates is possible.
Mode 1 or Mode 3 Baud Rate =
1 x Timer 2 Overflow Rate 16
Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles rather than every core machine cycle as before. It increments six times faster than Timer 1, and, therefore, baud rates six times faster are possible. Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible. Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in Timer/Counter 2 control SFR (T2CON, 0xC8). The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or
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ADE5166/ADE5169/ADE5566/ADE5569
TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 85. In this case, the baud rate is given by the following formula:
Mode 1 or Mode 3 Baud Rate = f CORE
Preliminary Technical Data
fCORE
FRACTIONAL /(1 + SBAUDF/64) DIVIDER TIMER 1/TIMER 2 Tx CLOCK TIMER 1/TIMER 2 Rx CLOCK 1 /2DIV + SBTH Rx CLOCK UARTBAUDEN Tx CLOCK
07411-081
0
(16 x [65536 - (RCAP2H : RCAP2L )])
UART Timer Generated Baud Rates
The high integer dividers in a UART block mean that high speed baud rates are not always possible. In addition, generating baud rates requires the exclusive use of a timer, rendering it unusable for other applications when the UART is required. To address this problem, each ADE5166/ADE5169/ADE5566/ADE5569 has a dedicated baud rate timer (UART timer) specifically for generating highly accurate baud rates. The UART timer can be used instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates, including 115,200 bps. This timer also allows a much wider range of baud rates to be obtained. In fact, every desired bit rate from 12 bps to 393,216 bps can be generated to within an error of 0.8%. The UART timer also frees up the other three timers, allowing them to be used for different applications. A block diagram of the UART timer is shown in Figure 84.
/32 1 UART TIMER Rx/Tx CLOCK 0
Figure 84. UART Timer, UART Baud Rate
Two SFRs, enhanced serial baud rate control SFR (SBAUDT, 0x9E) and UART timer fractional divider SFR (SBAUDF, 0x9D), are used to control the UART timer. SBAUDT is the baud rate control SFR; it sets up the integer divider (DIV) and the extended divider (SBTH) for the UART timer. The appropriate value to write to the DIV[2:0] and SBTH[1:0] bits can be calculated using the following formula where fCORE is defined in the POWCON SFR (see Table 25). Note that the DIV value must be rounded down to the nearest integer.
f CORE log 16 x Baud Rate DIV + SBTH = log(2)
TIMER 1 OVERFLOW
2 0 1 SMOD TL2 (8 BITS) T2 PIN C/ T2 = 1 1 TR2 NOTE: AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT RELOAD 16 RCAP2L RCAP2H 0 TCLK Tx CLOCK TH2 (8 BITS) TIMER 2 OVERFLOW 1 0 RCLK 16 Rx CLOCK
fCORE
CONTROL C/ T2 = 0
T2EX PIN CONTROL EXEN2
EXF 2
TIMER 2 INTERRUPT
Figure 85. Timer 2, UART Baud Rates
Rev. PrB | Page 126 of 148
07411-080
TRANSITION DETECTOR
Preliminary Technical Data
SBAUDF is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF can be calculated with the following formula:
f CORE SBAUDF = 64 x - 1 16 x 2 DIV + SBTH x Baud Rate
ADE5166/ADE5169/ADE5566/ADE5569
Rx
START D0 D1 D2 D3 D4 D5 D6 D7 STOP
RI FE EXTEN = 1
07411-082
Figure 86. UART Timing in Mode 1
Note that SBAUDF should be rounded to the nearest integer. After the values for DIV and SBAUDF are calculated, the actual baud rate can be calculated with the following formula:
Actual Baud Rate = f CORE SBAUDF 16 x 2 DIV + SBTH x 1 + 64
Rx
START
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP
RI FE EXTEN = 1
07411-083
For example, to obtain a baud rate of 9600 bps while operating at a core clock frequency of 4.096 MHz and with the PLL CD bits equal to 0,
Figure 87. UART Timing in Mode 2 and Mode 3
4,096,000 log 16 x 9600 DIV + SBTH = = 4.74 = 4 log(2)
Note that the DIV result is rounded down.
4,096,000 SBAUDF = 64 x - 1 = 42.67 = 0x2B 16 x 2 3 x 9600
The 8052 standard UART does not provide break error detection. However, for an 8-bit UART, a break error can be detected when the received character is 0, a null character, and when there is a no stop bit because the RB8 bit is low. Break error detection is not possible for a 9-bit 8052 UART because the stop bit is not recorded. The ADE5166/ADE5169/ADE5566/ADE5569 enhanced break error detection is available through the BE bit in the SBAUDT SFR. The 8052 standard UART prevents overwrite errors by not allowing a character to be received when the RI, receive interrupt flag, is set. However, it does not indicate if a character has been lost because the RI bit is set when the frame is received. The enhanced UART overwrite error detection provides this information. When the enhanced 8052 UART is enabled, a frame is received regardless of the state of the RI flag. If RI = 1 when a new byte is received, the byte in SCON is overwritten, and the overwrite error flag is set. The overwrite error flag is cleared when SBUF is read. The extended UART is enabled by setting the EXTEN bit in the configuration SFR (CFG, 0xAF).
Thus, the actual baud rate is 9570 bps, resulting in a 0.31% error.
UART ADDITIONAL FEATURES
Enhanced Error Checking
The extended UART provides frame error, break error, and overwrite error detection. Framing errors occur when a stop bit is not present at the end of the frame. A missing stop bit implies that the data in the frame may not have been received properly. Break error detection indicates whether the Rx line has been low for longer than a 9-bit frame. It indicates that the data just received, a 0 or null character, is not valid because the master has disconnected. Overwrite error detection indicates when the received data has not been read fast enough and, as a result, a byte of data has been lost. The 8052 standard UART offers frame-error checking for an 8-bit UART through the SM2 and RB8 bits. Setting the SM2 bit prevents frames without a stop bit from being received. The stop bit is latched into the RB8 bit in the serial communications control SFR (SCON, 0x98). This bit can be examined to determine if a valid frame was received. The 8052 does not, however, provide frame error checking for a 9-bit UART. This enhanced error checking functionality is available through the frame error bit, FE, in the enhanced serial baud rate control SFR (SBAUDT, 0x9E). The FE bit is set on framing errors for both 8-bit and 9-bit UARTs.
UART TxD Signal Modulation
There is an internal 38 kHz signal that can be OR'ed with the UART transmit signal for use in remote control applications (see the 38 kHz Modulation section). One of the events that can wake the MCU from sleep mode is activity on the RxD pin (see the 3.3 V Peripherals and Wake-Up Events section).
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ADE5166/ADE5169/ADE5566/ADE5569 UART2 SERIAL INTERFACE
The ADE5166/ADE5169/ADE5566/ADE5569 UART2 is an 8bit or 9-bit UART with variable baud rate Variable baud rates are defined by using an internal timer to generate any rate between 300 bauds/s and 115,200 bauds/s. The UART2 serial interface provided in the ADE5166/ADE5169/ ADE5566/ADE5569 is a full-duplex serial interface. It is also receive buffered, by storing the first received byte in a receive buffer until the reception of the second byte is complete. The physical interface to the UART is provided via the RxD2
Preliminary Technical Data
(P0.7/SS/T1) and TxD2 (P2.3/SDEN) pins, whereas the firmware interface is through the SFRs presented in Table 139. Both the serial port receive and transmit registers are accessed through the SBUF2 SFR (0xEB). Writing to SBUF2 loads the transmit register, and reading SBUF2 accesses a physically separate receive register. An enhanced UART mode is offered by using the UART timer and providing enhanced frame error, break error, and overwrite error detection. The SBAUD2 SFR is used to configure the UART2 timer and to indicate the enhanced UART2 errors.
UART SFR REGISTER LIST
Table 139. Serial Port 2 SFRs
SFR SCON2 SBUF2 SBAUD2 Address 0xE1 0xEB 0xEE Bit Addressable No No No Description Serial communications control (see Table 140) Serial Port 2 buffer (see Table 141) Enhance serial baud rate control (see Table 142)
Table 140. Serial Communications Control SFR (SCON2, 0xE1)
Bit 7 6 5 Mnemonic N/A EN-T8 OWE2 Default N/A 0 0 Description Reserved 9-bit UART, variable baud rate enable bit. When set, the UART2 is in 9-bit mode. Overwrite error. This bit is set when new data is received and RI = 1. It indicates that SBUF2 was not read before the next character was transferred in, causing the prior SBUF2 data to be lost. Write a zero to this bit to clear it. Frame error. This bit is set when the received frame does not have a valid stop bit. This bit is read only and updated every time a frame is received. Break error. This bit is set whenever the receive data line (Rx2) is low for longer than a full transmission frame, the time required for a start bit, eight data bits, a parity bit, and half a stop bit. This bit is updated every time a frame is received. Serial Port 2 receive enable bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. Serial Port 2 transmit interrupt flag. Set by hardware at the end of the eighth bit, TI2 must be cleared by user software. Serial Port 2 receive interrupt flag. Set by hardware at the end of the eighth bit, RI2 must be cleared by user software.
4 3
FE2 BE2
0 0
2 1 0
REN2 TI2 RI2
0 0 0
Table 141. Serial port 2 Buffer SFR (SBUF2, 0xEB)
Bit 7 to 0 Mnemonic SBUF2 Default 0 Description Serial Port 2 data buffer.
Table 142. Enhanced Serial baud rate control 2 SFR (SBAUD2, 0xEE)
Bit 7 6 5 4 to 3 Mnemonic TB8 RB8 SBF2 SBTH2.1, SBTH2.0 Default 0 0 Description Serial port transmit (Bit 9). The data loaded into TB8 is the ninth data bit transmitted in 9-bit mode. Serial port receiver (Bit 9). The ninth data bit received in 9-bit mode is latched into RB8. For 8-bit Mode, the stop bit is latched into RB8. Fractional divider boolean: When set, SBAUDF2 = 0x2B when clear, SBAUDF2 = 0x07. Extended divider ratio for baud rate setting as shown in Table 138.
0
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Preliminary Technical Data
Bit 2 to 0 Mnemonic DIV2.2, DIV2.1, DIV2.0 Default 0 Description Binary divider. DIV2.2 DIV2.1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
ADE5166/ADE5169/ADE5566/ADE5569
DIV2.0 0 1 0 1 0 1 0 1
Result Divide by 1. See Table 138 Divide by 2. See Table 138. Divide by 4. See Table 138. Divide by 8. See Table 138. Divide by 16. See Table 138. Divide by 32. See Table 138. Divide by 64. See Table 138. Divide by 128. See Table 138.
Table 143. Common Baud Rates Using UART2 Timer with a 4.096 MHz PLL Clock
Ideal Baud 115200 115200 57600 57600 38400 38400 38400 19200 19200 19200 19200 9600 9600 9600 9600 9600 4800 4800 4800 4800 4800 4800 2400 2400 2400 2400 2400 2400 2400 300 300 300 300 300 300 300 300 CD 0 1 0 1 0 1 2 0 1 2 3 0 1 2 3 4 0 1 2 3 4 5 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 SBTH2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 DIV2 1 0 2 1 2 1 0 3 2 1 0 4 3 2 1 0 5 4 3 2 1 0 6 5 4 3 2 1 0 7 7 7 6 5 4 3 2 SBAUDT 0x01 0x00 0x02 0x01 0x02 0x01 0x00 0x03 0x02 0x01 0x00 0x04 0x03 0x02 0x01 0x00 0x05 0x04 0x03 0x02 0x01 0x00 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x17 0x0F 0x07 0x06 0x05 0x04 0x03 0x02 SBF2 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SBAUDF2 0x07 0x07 0x07 0x07 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B 0x2B % Error + 0.16 + 0.16 + 0.16 + 0.16 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31 -0.31
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ADE5166/ADE5169/ADE5566/ADE5569
UART2 OPERATION MODE
The UART2 has two operation modes where each data byte (LSB first) is preceded by a start bit (0), followed by a stop bit (1). Therefore, each frame consists of 10 bits transmitted on TxD2 or received on RxD2. The baud rate is set by a dedicated timer for baud rate generation, UART2 Timer, which has a fractional divisor to precisely generate any baud rate. Transmission is initiated by a write to SBUF2. Next, a stop bit (1) is loaded into the 9th bit position of the transmit shift register. The data is output bit-by-bit until the stop bit appears on TxD2 and the transmit interrupt flag (TI2) is automatically set as shown in Figure 88.
TxD2 TI2 (SCON2.1)
07411-188
Preliminary Technical Data
9-Bit UART with Variable Baud Rate
9-bit mode is selected by setting EN-T8 in the serial communications control SFR (SCON, 0x98). In this mode, the UART2 serial port operates in 9-bit mode with a variable baud rate. The baud rate is set by a dedicated timer for baud rate generation, UART2 Timer, which has a fractional divisor to precisely generate any baud rate (see the UART Timer Generated Baud Rates section). The operation of the 9-bit UART2 is the same as for 9-bit mode for the UART1. In both modes, transmission is initiated by any instruction that uses SBUF2 as a destination register. Reception is initiated in 8-bit mode when RI = 0 and REN = 1. Reception is initiated in the 9-bit mode by the incoming start bit if REN = 1.
START BIT
STOP BIT D0 D1 D2 D3 D4 D5 D6 D7
UART BAUD RATE GENERATION
The baud rate is determined by the overflow rate of the dedicated baud rate generator, UART2 Timer, which has an integer and fractional divisor.
SET INTERRUPT (FOR EXAMPLE, READY FOR MORE DATA)
UART Timer Generated Baud Rates
The enhanced Serial Baud Rate Control 2 SFR (SBAUD2, 0xEE) is used to control UART2 Timer. SBAUD2 is the baud rate control SFR; it sets up the integer divider (DIV) and the extended divider (SBTH) for UART Timer. The desired value to write to the DIV[2:0] and SBTH[1:0] bits can be calculated using the following formula where fcore is defined in POWCON SFR. Note that the DIV value must be rounded down to the nearest integer.
f core log 16 x Baud Rate DIV2 + SBTH2 = log (2 ) SBAUDF2is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF2 can be calculated with the following formula:
f core SBAUDF2 = 64 x - 1 16 x 2 DIV 2 + SBTH 2 x Baud Rate
Figure 88. 8-Bit Variable Baud Rate
Reception is initiated when a 1-to-0 transition is detected on RxD2. Assuming that a valid start bit is detected, character reception continues. The eight data bits are clocked into the serial port shift register. All of the following conditions must be met at the time the final shift pulse is generated to receive a character:
*
*
If the extended UART is disabled (EXTEN = 0 in the CFG SFR), RI must be 0 to receive a character. This ensures that the data in the SBUF SFR is not overwritten if the last received character has not been read. If frame error checking is enabled by setting SM2, the received stop bit must be set to receive a character. This ensures that every character received comes from a valid frame, with both a start bit and a stop bit.
If any of these conditions are not met, the received frame is irretrievably lost, and the receive interrupt flag, RI2 is not set. If the received frame has met the preceding conditions, the following events occur:
* *
The eight bits in the receive shift register are latched into SBUF2. The receiver interrupt flag (RI2) is set.
Note that the SBAUDF2 can only take two values, 0x87 or 0xAB, by clearing or setting the SBF2 bit, respectively, in the SBAUD2 SFR. These values were chosen to provide an accurate baud rate for 300, 2400, 4800, 9600, 19200, 38400, 57600, and 115,200 bps. Once DIV2 and SBAUDF2 are calculated, the actual baud rate can be calculated with the following formula: Actual Baud Rate =
Transmission is initiated by any instruction that uses SBUF2 as a destination register. Reception is initiated by the incoming start bit if REN2 = 1.
f core SBAUDF 2 16 x 2 DIV 2 + SBTH 2 1 + 64
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Preliminary Technical Data
For example, to get a baud rate of 9600 while operating at a core clock frequency of 4.096 MHz, with the PLL CD bits equal to 0, DIV2 + SBTH2 = log(4,096,000/(16 x 9600))/log2 = 4.74 = 4 Note that the DIV result is rounded down. SBAUDF2 = 64 x (4,096,000/(16 x 23 x 9600) - 1) = 42.67 = 0x2B Therefore, the actual baud rate is 9570 bps, which gives an error of 0.31%.
ADE5166/ADE5169/ADE5566/ADE5569
UART ADDITIONAL FEATURES
Enhanced Error Checking
The extended UART2 provides frame error, break error and overwrite error detection. Framing errors occur when a stop bit is not present at the end of the frame. A missing stop bit implies that the data in the frame may not have been received properly. Break error detection indicates if the Rx line has been low for longer than a 9-bit frame. It indicates that the data just received, a zero, or NULL character, is not valid because the master has disconnected. Overwrite error detection indicates if the received data isn't read fast enough and as result, a byte of data has been lost.
UART2 TxD2 signal modulation
There is an internal 38 kHz signal that can be read with the UART2 transmit signal for use in remote control applications.
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ADE5166/ADE5169/ADE5566/ADE5569 SERIAL PERIPHERAL INTERFACE (SPI)
The ADE5166/ADE5169/ADE5566/ADE5569 integrate a complete hardware serial peripheral interface on-chip. The SPI is full duplex so that eight bits of data are synchronously transmitted and simultaneously received. This SPI implementation is double buffered, allowing users to read the last byte of received data while a new byte is shifted in. The next byte to be transmitted can be loaded while the current byte is shifted out. The SPI port can be configured for master or slave operation. The physical interface to the SPI is via the MISO (P0.5),
Preliminary Technical Data
MOSI (P0.4), SCLK (P0.6), and SS (P0.7) pins, while the firmware interface is via the SPI Configuration SFR 1 (SPIMOD1, 0xE8), the SPI Configuration SFR 2 (SPIMOD2, 0xE9), the SPI interrupt status SFR (SPISTAT, 0xEA), the SPI/I2C transmit buffer SFR (SPI2CTx, 0x9A), and the SPI/I2C receive buffer SFR (SPI2CRx, 0x9B). Note that the SPI pins are shared with the I2C pins. Therefore, the user can enable only one interface at a time. The SCPS bit in the configuration SFR (CFG, 0xAF) selects which peripheral is active.
SPI REGISTERS
Table 144. SPI SFR List
SFR Address 0x9A 0x9B 0xE8 0xE9 0xEA Mnemonic SPI2CTx SPI2CRx SPIMOD1 SPIMOD2 SPISTAT R/W W R R/W R/W R/W Length (Bits) 8 8 8 8 8 Default 0 0 0x10 0 0 Description SPI/I2C transmit buffer (see Table 145). SPI/I2C receive buffer (see Table 146). SPI Configuration SFR 1 (see Table 147). SPI Configuration SFR 2 (see Table 148). SPI interrupt status (see Table 149).
Table 145. SPI/I2C Transmit Buffer SFR (SPI2CTx, 0x9A)
Bit 7 to 0 Mnemonic SPI2CTx Default 0 Description SPI or I2C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit FIFO input. When a write is requested, the FIFO output is sent on the SPI or I2C bus.
Table 146. SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B)
Bit 7 to 0 Mnemonic SPI2CRx Default 0 Description SPI or I2C receive buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is transferred to the SPI2CRx SFR. A new data byte from the SPI or I2C bus is written to the FIFO input.
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Preliminary Technical Data
Table 147. SPI Configuration SFR 1 (SPIMOD1, 0xE8)
Bit 7 to 6 5 Address 0xEF to 0xEE 0xED Mnemonic Reserved INTMOD Default 0 0
ADE5166/ADE5169/ADE5566/ADE5569
Description Reserved. SPI interrupt mode. INTMOD Result 0 SPI interrupt is set when SPI Rx buffer is full. 1 SPI interrupt is set when SPI Tx buffer is empty. Master mode, SS output control (see Figure 89). Result The SS pin is held low while this bit is cleared. This allows manual chip select control using the SS pin. 1 Single Byte Read or Write. The SS pin goes low during a single byte transmission and then returns high. Continuous Transfer. The SS pin goes low during the duration of the multibyte continuous transfer and then returns high. Slave mode, SS input enable. When this bit is set to Logic 1, the SS pin is defined as the slave select input pin for the SPI slave interface. Receive buffer overflow write enable. RxOFW Result 0 If the SPI2CRx SFR has not been read when a new data byte is received, the new byte is discarded. 1 If the SPI2CRx SFR has not been read when a new data byte is received, the new byte overwrites the old data. Master mode, SPI SCLK frequency. SPIR[1:0] Result 00 fCORE/8 = 512 kHz (if fCORE = 4.096 MHz). 01 fCORE/16 = 256 kHz (if fCORE = 4.096 MHz). 10 fCORE/32 = 128 kHz (if fCORE = 4.096 MHz). 11 fCORE/64 = 64 kHz (if fCORE = 4.096 MHz). AUTO_SS 0
4
0xEC
AUTO_SS
1
3
0xEB
SS_EN
0
2
0xEA
RxOFW
0
1 to 0
0xE9 to 0xE8
SPIR[1:0]
0
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ADE5166/ADE5169/ADE5566/ADE5569
Table 148. SPI Configuration SFR 2 (SPIMOD2, 0xE9)
Bit 7 Mnemonic SPICONT Default 0
Preliminary Technical Data
6
SPIEN
0
5
SPIODO
0
4
SPIMS_b
0
3
SPICPOL
0
2
SPICPHA
0
1
SPILSBF
0
0
TIMODE
1
Description Master mode, SPI continuous transfer mode enable bit. SPICONT Result 0 The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer can be initiated after a stalled period. 1 The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR. SS remains asserted until the SPI2CTx SFR and the transmit shift registers are empty. SPI interface enable bit. SPIEN Result 0 The SPI interface is disabled. 1 The SPI interface is enabled. SPI open-drain output configuration bit. SPIODO Result 0 Internal pull-up resistors are connected to the SPI outputs. 1 The SPI outputs are open drain and need external pull-up resistors. The pull-up voltage should not exceed the specified operating voltage. SPI master mode enable bit. SPIMS_b Result 0 The SPI interface is defined as a slave. 1 The SPI interface is defined as a master. SPI clock polarity configuration bit (see Figure 91). SPICPOL Result 0 The default state of SCLK is low, and the first SCLK edge is rising. Depending on the SPICPHA bit, the SPI data output changes state on the falling or rising edge of SCLK while the SPI data input is sampled on the rising or falling edge of SCLK. 1 The default state of SCLK is high, and the first SCLK edge is falling. Depending on the SPICPHA bit, the SPI data output changes state on the rising or falling edge of SCLK while the SPI data input is sampled on the falling or rising edge of SCLK. SPI clock phase configuration bit (see Figure 91). SPICPHA Result 0 The SPI data output changes state when SS goes low at the second edge of SCLK and then every two subsequent edges, whereas the SPI data input is sampled at the first SCLK edge and then every two subsequent edges. 1 The SPI data output changes state at the first edge of SCLK and then every two subsequent edges, whereas the SPI data input is sampled at the second SCLK edge and then every two subsequent edges. Master mode, LSB first configuration bit. SPILSBF Result 0 The MSB of the SPI outputs is transmitted first. 1 The LSB of the SPI outputs is transmitted first. Transfer and interrupt mode of the SPI interface. TIMODE Result 1 This bit must be left set for proper operation.
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Preliminary Technical Data
Table 149. SPI Interrupt Status SFR (SPISTAT, 0xEA)
Bit 7 Mnemonic BUSY Default 0
ADE5166/ADE5169/ADE5566/ADE5569
6
MMERR
0
5
SPIRxOF
0
4
SPIRxIRQ
0
3 2 1
SPIRxBF SPITxUF SPITxIRQ
0 0 0
Description SPI peripheral busy flag. BUSY Result 0 The SPI peripheral is idle. 1 The SPI peripheral is busy transferring data in slave or master mode. SPI multimaster error flag. MMERR Result 0 A multiple master error has not occurred. 1 If the SS_EN bit is set, enabling the slave select input and asserting the SS pin while the SPI peripheral is transferring data as a master, this flag is raised to indicate the error. Write a 0 to this bit to clear it. SPI receive overflow error flag. Reading the SPI2CRx SFR clears this bit. SPIRxOF TIMODE Result 0 X The SPI2CRx register contains valid data. 1 1 This bit is set if the SPI2CRx register is not read before the end of the next byte transfer. If the RxOFW bit is set and this condition occurs, SPI2CRx is overwritten. SPI receive mode interrupt flag. Reading the SPI2CRx SFR clears this bit. SPIRxIRQ TIMODE Result 0 X The SPI2CRx register does not contain new data. 1 0 This bit is set when the SPI2CRx register contains new data. If the SPI/I2C interrupt is enabled, an interrupt is generated when this bit is set. If the SPI2CRx register is not read before the end of the current byte transfer, the transfer stops and the SS pin is deasserted. 1 1 The SPI2CRx register contains new data. Status bit for SPI Rx buffer. When set, the Rx FIFO is full. A read of the SPI2CRx clears this flag. Status bit for SPI Tx buffer. When set, the Tx FIFO is underflowing and data can be written into SPI2CTx. Write a 0 to this bit to clear it. SPI transmit mode interrupt flag. Writing new data to the SPI2CTx SFR clears this bit. SPITxIRQ TIMODE Result 0 X The SPI2CTx register is full. 1 0 The SPI2CTx register is empty. 1 1 This bit is set when the SPI2CTx register is empty. If the SPI/I2C interrupt is enabled, an interrupt is generated when this bit is set. If new data is not written into the SPI2CTx SFR before the end of the current byte transfer, the transfer stops, and the SS pin is deasserted. Write a 0 to this bit to clear it. Status bit for SPI Tx buffer. When set, the SPI Tx buffer is full. Write a 0 to this bit to clear it.
0
SPITxBF
0
SPI PINS
MISO (Master In, Slave Out Data I/O Pin)
The MISO pin is configured as an input line in master mode and as an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte-wide (8-bit) serial data, MSB first.
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data being transmitted and received through the MOSI and MISO data lines. The SCLK pin is configured as an output in master mode and as an input in slave mode. In master mode, the bit rate, polarity, and phase of the clock are controlled by the SPI Configuration SFR 1 (SPIMOD1, 0xE8) and SPI Configuration SFR 2 (SPIMOD2, 0xE9). In slave mode, the SPI Configuration SFR 2 (SPIMOD2, 0xE9) must be configured with the phase and polarity of the expected input clock. In both master and slave modes, the data is transmitted on one edge of the SCLK signal and sampled on the other. It is important, therefore, that the SPICPHA and SPICPOL bits be configured the same for the master and slave devices.
MOSI (Master Out, Slave In Pin)
The MOSI pin is configured as an output line in master mode and as an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte-wide (8-bit) serial data, MSB first.
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ADE5166/ADE5169/ADE5566/ADE5569
SS (Slave Select Pin)
In SPI slave mode, a transfer is initiated by the assertion of SS low. The SPI port then transmits and receives 8-bit data until the data is concluded by the deassertion of SS according to the SPICON bit setting. In slave mode, SS is always an input. In SPI master mode, the SS can be used to control data transfer to a slave device. In the automatic slave select control mode, the SS is asserted low to select the slave device and then raised to deselect the slave device after the transfer is complete. Automatic slave select control is enabled by setting the AUTO_SS bit in the SPI Configuration SFR 1 (SPIMOD1, 0xE8). In a multimaster system, the SS can be configured as an input so that the SPI peripheral can operate as a slave in some situations and as a master in others. In this case, the slave selects for the slaves controlled by this SPI peripheral should be generated with general I/O pins.
Preliminary Technical Data
Figure 89 shows the SPI output for certain automatic chip select and continuous mode selections. Note that if the continuous mode is not used, a short delay is inserted between transfers.
SS SCLK
AUTO_SS = 1 SPICONT = 1
DIN
DIN1
DIN2
DOUT
DOUT1
DOUT2
SS SCLK
SPI MASTER OPERATING MODES
The double buffered receive and transmit registers can be used to maximize the throughput of the SPI peripheral by continuously streaming out data in master mode. The continuous transmit mode is designed to use the full capacity of the SPI. In this mode, the master transmits and receives data until the SPI/I2C transmit buffer SFR (SPI2CTx, 0x9A) is empty at the start of a byte transfer. Continuous mode is enabled by setting the SPICONT bit in the SPI Configuration SFR 2 (SPIMOD2, 0xE9). The SPI peripheral also offers a single byte read/write function. In master mode, the type of transfer is handled automatically, depending on the configuration of the SPICONT bit in the SPI Configuration SFR 2 (SPIMOD2, 0xE9). The following procedures show the sequence of events that should be performed for each master operating mode. Based on the SS configuration, some of these events take place automatically.
AUTO_SS = 1 SPICONT = 0
DIN
DIN1
DIN2
DOUT
DOUT1
DOUT2
SS SCLK
AUTO_SS = 0 SPICONT = 0 (MANUAL SS CONTROL)
DIN
DIN1
DIN2
DOUT
DOUT1
DOUT2
Figure 89. Automatic Chip Select and Continuous Mode Output
Procedures for Using SPI as a Master Single Byte Write Mode, SPICONT (SPIMOD2[7]) = 0
1. 2. 3. 4. 5. Write to SPI2CTx SFR. SS is asserted low and a write routine is initiated. SPITxIRQ interrupt flag is set when the SPI2CTx register is empty. SS is deasserted high. Write to SPI2CTx SFR to clear the SPITxIRQ interrupt flag.
Note that reading the content of the SPI/I2C receive buffer SFR (SPI2CRx, 0x9B) should be done using a 2-cycle instruction set, such as MOV A or SPI2CRX. Using a 3-cycle instruction, such as MOV 0x3D or SPI2CRX, does not transfer the right information into the target register.
Continuous Mode, SPICONT (SPIMOD2[7]) = 1
1. 2. 3. 4. 5. 6. 7. Write to SPI2CTx SFR. SS is asserted low and write routine is initiated. Wait for the SPITxIRQ interrupt flag to write to SPI2CTx SFR. Transfer continues until the SPI2CTx register and transmit shift registers are empty. SPITxIRQ interrupt flag is set when the SPI2CTx register is empty. SS is deasserted high. Write to SPI2CTx SFR to clear the SPITxIRQ interrupt flag.
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07411-084
Preliminary Technical Data
SPI INTERRUPT AND STATUS FLAGS
The SPI interface has several status flags that indicate the status of the double-buffered receive and transmit registers. Figure 90 shows when the status and interrupt flags are raised. The transmit interrupt occurs when the transmit shift register is loaded with the data in the SPI/I2C transmit buffer SFR (SPI2CTx, 0x9A) register. If the SPI master is in transmit operating mode, and the SPI/I2C transmit buffer SFR (SPI2CTx, 0x9A) register has not been written with new data by the beginning of the next byte transfer, the transmit operation stops. When a new byte of data is received in the SPI/I C receive buffer SFR (SPI2CRx, 0x9B) register, the SPI receive interrupt flag is raised. If the data in the SPI/I2C receive buffer SFR
SCLK (SPICPOL = 1) SCLK (SPICPOL = 0)
2
ADE5166/ADE5169/ADE5566/ADE5569
(SPI2CRx, 0x9B) is not read before new data is ready to be loaded into the SPI/I2C receive buffer SFR (SPI2CRx, 0x9B), an overflow condition has occurred. This overflow condition, indicated by the SPIRxOF flag, forces the new data to be discarded or overwritten if the RxOFW bit is set.
SPITx SPITxIRQ = 1 TRANSMIT SHIFT REGISTER SPIRx SPIRxIRQ = 1 RECEIVE SHIFT REGISTER
SPITx (EMPTY) STOPS TRANSFER IF TIMODE = 1 TRANSMIT SHIFT REGISTER
SPIRx (FULL)
07411-085
SPIRxOF = 1
RECEIVE SHIFT REGISTER
Figure 90. SPI Receive and Transmit Interrupt and Status Flags
SS
MISO
? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MOSI SPICPHA = 1 SPIRx AND SPITx FLAGS WITH INTMOD = 1 SPIRx AND SPITx FLAGS WITH INTMOD = 0
? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MISO
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
MOSI SPICPHA = 0 SPIRx AND SPITx FLAGS WITH INTMOD = 1
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
Figure 91. SPI Timing Configurations
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07411-086
SPIRx AND SPITx FLAGS WITH INTMOD = 0
ADE5166/ADE5169/ADE5566/ADE5569 I2C-COMPATIBLE INTERFACE
The ADE5166/ADE5169/ADE5566/ADE5569 support a fully licensed I2C interface. The I2C interface is implemented as a full hardware master. SDATA is the data I/O pin, and SCLK is the serial clock. These two pins are shared with the MOSI and SCLK pins of the on-chip SPI interface. Therefore, the user can enable only one interface or the other on these pins at any given time. The SCPS bit in the configuration SFR (CFG, 0xAF) selects which peripheral is active. The two pins used for data transfer, SDATA and SCLK, are configured in a wire-AND format that allows arbitration in a multimaster system. The transfer sequence of an I C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. If the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle.
2
Preliminary Technical Data
The bit rate is defined in the I2CMOD SFR as follows: f SCLK = f CORE 16 x 2 I 2CR[1:0]
SLAVE ADDRESSES
The I2C slave address SFR (I2CADR, 0xE9) contains the slave device ID. The LSB of this register contains a read/write request. A write to this SFR starts the I2C communication.
I2C REGISTERS
The I2C peripheral interface consists of five SFRs. * * * * * I2CMOD SPI2CSTAT I2CADR SPI2CTx SPI2CRx
SERIAL CLOCK GENERATION
The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (256 kHz) or standard mode (32 kHz).
Table 150. I2C SFR List
SFR Address 0x9A 0x9B 0xE8 0xE9 0xEA Mnemonic SPI2CTx SPI2CRx I2CMOD I2CADR SPI2CSTAT R/W W R R/W R/W R/W Length 8 8 8 8 8
Because the SPI and I2C serial interfaces share the same pins, they also share the same SFRs, such as the SPI2CTx and SPI2CRx SFRs. In addition, the I2CMOD, I2CADR, and SPI2CSTAT SFRs are shared with the SPIMOD1, SPIMOD2, and SPISTAT SFRs, respectively.
Default 0 0 0 0
Description SPI/I2C transmit buffer (see Table 145). SPI/I2C receive buffer (see Table 146). I2C mode (see Table 151). I2C slave address (see Table 152). I2C interrupt status register (see Table 153).
Table 151. I2C Mode SFR (I2CMOD, 0xE8)
Bit 7 6 to 5 Address 0xEF 0xEE to 0xED Mnemonic I2CEN I2CR[1:0] Default 0 0 Description I2C enable bit. When this bit is set to Logic 1, the I2C interface is enabled. A write to the I2CADR SFR starts a communication. I2C SCLK frequency. I2CR[1:0] Result 00 fCORE/16 = 256 kHz if fCORE = 4.096 MHz. 01 fCORE/32 = 128 kHz if fCORE = 4.096 MHz. 10 fCORE/64 = 64 Hz if fCORE = 4.096 MHz. 11 fCORE/128= 32 kHz if fCORE = 4.096 MHz. Configures the length of the I2C received FIFO buffer. The I2C peripheral stops when I2CRCT[4:0] + 1 byte have been read, or if an error occurs.
4 to 0
0xEC to 0xE8
I2CRCT[4:0]
0
Table 152. I2C Slave Address SFR (I2CADR, 0xE9)
Bit 7 to 1 0 Mnemonic I2CSLVADR I2CR_W Default 0 0 Description Address of the I2C slave being addressed. Writing to this register starts the I2C transmission (read or write). Command bit for read or write. When this bit is set to Logic 1, a read command is transmitted on the I2C bus. Data from the slave in the SPI2CRx SFR is expected after a command byte. When this bit is set to Logic 0, a write command is transmitted on the I2C bus. Data to slave is expected in the SPI2CTx SFR.
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Preliminary Technical Data
Table 153. I2C Interrupt Status Register SFR (SPI2CSTAT, 0xEA)
Bit 7 6 Mnemonic I2CBUSY I2CNOACK Default 0 0
ADE5166/ADE5169/ADE5566/ADE5569
5 4 3 to 2
I2CRxIRQ I2CTxIRQ I2CFIFOSTAT[1:0]
0 0 0
1 0
I2CACC_ERR I2CTxWR_ERR
0 0
Description This bit is set to Logic 1 when the I2C interface is used. When set, the Tx FIFO is emptied. I2C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device does not send an acknowledgement. The I2C communication is stopped after this event. Write a 0 to this bit to clear it. I2C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty. Write a 0 to this bit to clear it. I2C transmit interrupt. This bit is set to Logic 1 when the transmit FIFO is empty. Write a 0 to this bit to clear it. Status Bits for 3- or 4-byte deep I2C FIFO. The FIFO monitored in these two bits is the one currently used in I2C communication (receive or transmit) because only one FIFO is active at a time. I2CFIFOSTAT[1:0] Result 00 FIFO empty 01 Reserved 10 FIFO half full 11 FIFO full Set when trying to write and read at the same time. Write a 0 to this bit to clear it. Set when write was attempted when I2C transmit FIFO was full. Write a 0 to this bit to clear it.
READ AND WRITE OPERATIONS
1 SCLK 9 1 9 1 9
SDATA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK BY SLAVE
D7
D6
D5
D4
D3
D2
D1
D0 ACK BY MASTER
D7
D6
D5
D4
D3
D2
D1
D0
07411-087
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE 1 FROM MASTER
FRAME N + 1 DATA BYTE N FROM SLAVE
NACK BY STOP BY MASTER MASTER
Figure 92. I2C Read Operation
1 SCLK
9
1
9
SDATA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK BY SLAVE
D7
D6
D5
D4
D3
D2
D1
D0
07411-088
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE 1 FROM MASTER
ACK BY SLAVE
STOP BY MASTER
Figure 93. I2C Write Operation
Figure 92 and Figure 93 depict I2C read and write operations, respectively. Note that the LSB of the I2CADR register is used to select whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated automatically by the I2C peripheral. The master generated NACK (no acknowledge) before the end of a read operation is also automatically generated after I2CRCT[4:0] have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a stop at the end of the read or write operation, the master generates a start condition and continues with the next communication.
Reading the SPI/I2C Receive Buffer SFR (SPI2CRx, 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle instruction, such as
Mov a, spi2crx or Mov R0, spi2crx.
A 3-cycle instruction such as
Mov 3dh, spi2crx
does not transfer the right data into RAM Address 0x3D.
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ADE5166/ADE5169/ADE5566/ADE5569
I2C RECEIVE AND TRANSMIT FIFOS
The I2C peripheral has a 4-byte receive FIFO and a 4-byte transmit FIFO. The buffers reduce the overhead associated with using the I2C peripheral. Figure 94 shows the operation of the I2C receive and transmit FIFOs. The Tx FIFO can be loaded with four bytes to be transmitted to the slave at the beginning of a write operation. When the transmit FIFO is empty, the I2C transmit interrupt flag is set, and the PC vectors to the I2C interrupt vector if this interrupt is enabled. If a new byte is not loaded into the Tx FIFO before it is needed in the transmit shift register, the communication stops. An error, such as not receiving an acknowledge, also causes the communication to terminate. In case of an error during a write operation, the Tx FIFO is flushed. The Rx FIFO allows four bytes to be read in from the slave before the MCU has to read the data. A receive interrupt can be generated after each byte is received or when the Rx FIFO
Preliminary Technical Data
is full. If the peripheral is reading from a slave address, the communication stops once the number of received bytes equals the number set in I2CRCT[4:0]. An error, such as not receiving an acknowledge, also causes the communication to terminate.
CODE TO FILL Tx FIFO: MOV MOV MOV MOV I2CTx, I2CTx, I2CTx, I2CTx, TxDATA1 TxDATA2 TxDATA3 TxDATA4 I2CTx CODE TO READ Rx FIFO: MOV A, MOV A, MOV A, MOV A, I2CRx; I2CRx; I2CRx; I2CRx; RESULT: A = RxDATA1 RESULT: A = RxDATA2 RESULT: A = RxDATA3 RESULT: A = RxDATA4 I2CRx
TxDATA4 4-BYTE FIFO TxDATA3 TxDATA2 TxDATA1 4-BYTE FIFO
RxDATA1 RxDATA2 RxDATA3 RxDATA4
07411-089
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
Figure 94. I2C FIFO Operation
Rev. PrB | Page 140 of 148
Preliminary Technical Data I/O PORTS
PARALLEL I/O
The ADE5166/ADE5169/ADE5566/ADE5569 use three input/ output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of driving an LCD or performing alternate functions for the peripherals available on-chip. In general, when a peripheral is enabled, the pins associated with it cannot be used as a general-purpose I/O. The I/O port can be configured through the SFRs in Table 154.
Table 154. I/O Port SFRs
SFR P0 P1 P2 EPCFG PINMAP0 PINMAP1 PINMAP2 Address 0x80 0x90 0xA0 0x9F 0xB2 0xB3 0xB4 Bit Addressable Yes Yes Yes No No No No Description Port 0 register Port 1 register Port 2 Register Extended port configuration Port 0 weak pull-up enable Port 1 weak pull-up enable Port 2 weak pull-up enable
ADE5166/ADE5169/ADE5566/ADE5569
Weak Internal Pull-Ups Enabled
A pin with weak internal pull-up enabled is used as an input by writing a 1 to the pin. The pin is pulled high by the internal pullups, and the pin is read using the circuitry shown in Figure 95. If the pin is driven low externally, it sources current because of the internal pull-ups. A pin with internal pull-up enabled is used as an output by writing a 1 or a 0 to the pin to control the level of the output. If a 0 is written to the pin, it drives a logic low output voltage (VOL) and is capable of sinking 1.6 mA.
Open Drain (Weak Internal Pull-Ups Disabled)
When the weak internal pull-up on a pin is disabled, the pin becomes open drain. Use this open-drain pin as a high impedance input by writing a 1 to the pin. The pin is read using the circuitry shown in Figure 95. The open-drain option is preferable for inputs because it draws less current than the internal pull-ups that were enabled.
38 kHz Modulation
Every ADE5166/ADE5169/ADE5566/ADE5569 provides a 38 kHz modulation signal. The 38 kHz modulation is accomplished by internally XOR'ing the level written to the I/O pin with a 38 kHz square wave. Then, when a 0 is written to the I/O pin, it is modulated as shown in Figure 96.
LEVEL WRITTEN TO MOD38 38kHz MODULATION SIGNAL 38kHz MODULATED OUTPUT PIN
07411-091
The three bidirectional I/O ports have internal pull-ups that can be enabled or disabled individually for each pin. The internal pull-ups are enabled by default. Disabling an internal pull-up causes a pin to become open drain. Weak internal pull-ups are configured through the PINMAPx SFRs. Figure 95 shows a typical bit latch and I/O buffer for an I/O pin. The bit latch (one bit in the SFR of each port) is represented as a Type D flip-flop, which clocks in a value from the internal bus in response to a write-to-latch signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a read latch signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a read pin signal from the CPU. Some instructions that read a port activate the read latch signal, and others activate the read pin signal. See the Read-Modify-Write Instructions section for details.
DVDD
Figure 96. 38 kHz Modulation
Uses for this 38 kHz modulation include IR modulation of a UART transmit signal or a low power signal to drive an LED. The modulation can be enabled or disabled with the MOD38EN bit in the CFG SFR. The 38 kHz modulation is available on eight pins, selected by the MOD38[7:0] bits in the extended port configuration SFR (EPCFG, 0x9F).
READ LATCH INTERNAL BUS WRITE TO LATCH
ALTERNATE OUTPUT FUNCTION
INTERNAL PULL-UP CLOSED: PINMAPx.x = 0 OPEN: PINMAPx.x = 1 Px.x PIN
D
Q
CL Q LATCH
Figure 95. Port 0 Bit Latch and I/O Buffer
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07411-090
READ PIN
ALTERNATE INPUT FUNCTION
ADE5166/ADE5169/ADE5566/ADE5569
I/O REGISTERS
Table 155. Extended Port Configuration SFR (EPCFG, 0x9F)
Bit 7 6 5 4 3 2 1 0 Mnemonic MOD38_FP21 MOD38_FP22 MOD38_FP23 MOD38_TxD MOD38_CF1 MOD38_SSb MOD38_MISO MOD38_CF2 Default 0 0 0 0 0 0 0 0
Preliminary Technical Data
Description Enable 38 kHz modulation on P1.6/FP21 pin. Enable 38 kHz modulation on P1.5/FP22 pin. Enable 38 kHz modulation on P1.4/T2/FP23 pin. Enable 38 kHz modulation on P1.1/TxD pin. Enable 38 kHz modulation on P0.2/CF1/RTCCAL pin. Enable 38 kHz modulation on P0.7/SS/T1pin. Enable 38 kHz modulation on P0.5/MISO/ZX pin. Enable 38 kHz modulation on P0.3/CF2 pin.
Table 156. Port 0 Weak Pull-Up Enable SFR (PINMAP0, 0xB2)
Bit 7 6 5 4 3 2 1 0 Mnemonic PINMAP0.7 PINMAP0.6 PINMAP0.5 PINMAP0.4 PINMAP0.3 PINMAP0.2 PINMAP0.1 PINMAP0.0 Default 0 0 0 0 0 0 0 0 Description The weak pull-up on P0.7 is disabled when this bit is set. The weak pull-up on P0.6 is disabled when this bit is set. The weak pull-up on P0.5 is disabled when this bit is set. The weak pull-up on P0.4 is disabled when this bit is set. The weak pull-up on P0.3 is disabled when this bit is set. The weak pull-up on P0.2 is disabled when this bit is set. The weak pull-up on P0.1 is disabled when this bit is set. The weak pull-up on P0.0 is disabled when this bit is set.
Table 157. Port 1 Weak Pull-Up Enable SFR (PINMAP1, 0xB3)
Bit 7 6 5 4 3 2 1 0 Mnemonic PINMAP1.7 PINMAP1.6 PINMAP1.5 PINMAP1.4 PINMAP1.3 PINMAP1.2 PINMAP1.1 PINMAP1.0 Default 0 0 0 0 0 0 0 0 Description The weak pull-up on P1.7 is disabled when this bit is set. The weak pull-up on P1.6 is disabled when this bit is set. The weak pull-up on P1.5 is disabled when this bit is set. The weak pull-up on P1.4 is disabled when this bit is set. The weak pull-up on P1.3 is disabled when this bit is set. The weak pull-up on P1.2 is disabled when this bit is set. The weak pull-up on P1.1 is disabled when this bit is set. The weak pull-up on P1.0 is disabled when this bit is set.
Table 158. Port 2 Weak Pull-Up Enable SFR (PINMAP2, 0xB4)
Bit 7 to 6 5 4 3 2 1 0 Mnemonic Reserved PINMAP2.5 Reserved PINMAP2.3 PINMAP2.2 PINMAP2.1 PINMAP2.0 Default 0 0 0 0 0 0 0 Description Reserved. Should be left cleared. The weak pull-up on RESET is disabled when this bit is set. Reserved. Should be left cleared. Reserved. Should be left cleared. The weak pull-up on P2.2 is disabled when this bit is set. The weak pull-up on P2.1 is disabled when this bit is set. The weak pull-up on P2.0 is disabled when this bit is set.
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Preliminary Technical Data
Table 159. Port 0 SFR (P0, 0x80)
Bit 7 6 5 4 3 2 1 0
1
ADE5166/ADE5169/ADE5566/ADE5569
Description1 This bit reflects the state of P0.7/SS/T1/RxD2 pin. It can be written or read. This bit reflects the state of P0.6/SCLK/T0 pin. It can be written or read. This bit reflects the state of P0.5/MISO/ZX pin. It can be written or read. This bit reflects the state of P0.4/MOSI/SDATA pin. It can be written or read. This bit reflects the state of P0.3/CF2 pin. It can be written or read. This bit reflects the state of P0.2/CF1 pin. It can be written or read. This bit reflects the state of P0.1/FP19/RTCCAL pin. It can be written or read. This bit reflects the state of BCTRL/INT1/P0.0 pin. It can be written or read.
Address 0x87 0x86 0x85 0x84 0x83 0x82 0x81 0x80
Mnemonic T1 T0 ZX CF2 CF1 INT1
Default 1 1 1 1 1 1 1 1
When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Table 160. Port 1 SFR (P1, 0x90)
Bit 7 6 5 4 3 2 1 0
1
Address 0x97 0x96 0x95 0x94 0x93 0x92 0x91 0x90
Mnemonic
T2 T2EX ZX1 TxD RxD
Default 1 1 1 1 1 1 1 1
Description1 This bit reflects the state of P1.7/FP20 pin. It can be written or read. This bit reflects the state of P1.6/FP21 pin. It can be written or read. This bit reflects the state of P1.5/FP22 pin. It can be written or read. This bit reflects the state of P1.4/T2/FP23 pin. It can be written or read. This bit reflects the state of P1.3/T2EX/FP24 pin. It can be written or read. This bit reflects the state of P1.2/FP25/ZX pin. It can be written or read. This bit reflects the state of P1.1/TxD pin. It can be written or read. This bit reflects the state of P1.0/RxD pin. It can be written or read.
When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Table 161. Port 2 SFR (P2, 0xA0)
Bit 7 to 4 3 2 1 0
1
Address 0x97 to 0x94 0x93 0x92 0x91 0x90
Mnemonic P2.3 P2.2 P2.1 P2.0
Default 0x1F 1 1 1 1
Description1 These bits are unused and should remain set. This bit reflects the state of SDEN/P2.3/TxD2 pin. It can be written only. This bit reflects the state of P2.2/FP16 pin. It can be written or read. This bit reflects the state of P2.1/FP17 pin. It can be written or read. This bit reflects the state of P2.0/FP18 pin. It can be written or read.
When an alternate function is chosen for a pin of this port, the bit controlling this pin should always be set.
Rev. PrB | Page 143 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Table 162. Port 0 Alternate Functions
Pin No. P0.0 Alternate Function BCTRL external battery control input INT1 external interrupt INT1 wake-up from PSM2 operating mode P0.1 P0.2 P0.3 P0.4 FP19 LCD segment pin CF1 ADE calibration frequency output CF2 ADE calibration frequency output MOSI SPI data line SDATA I2C data line P0.5 MISO SPI data line Zero Crossing Detection 2 SCLK serial clock for I2C or SPI T0 Timer0 input P0.7 SS SPI slave select input for SPI in slave mode SS SPI slave select output for SPI in master mode T1 Timer 1 input RxD2 receiver data input for UART2
Preliminary Technical Data
Alternate Function Enable Set INT1PROG[2:0] = x01 in the interrupt pins configuration SFR (INTPR, 0xFF). Set EX1 in the Interrupt Enable SFR (IE, 0xA8). Set INT1PROG[2:0] = 11x in the interrupt pins configuration SFR (INTPR, 0xFF). Set FP19EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Clear the DISCF1 bit in the ADE energy measurement internal MODE1 register (0x0B). Clear the DISCF2 bit in the ADE energy measurement internal MODE1 register (0x0B). Set the SCPS bit in the configuration SFR (CFG, 0xAF) and set the SPIEN bit in SPI Configuration SFR 2 (SPIMOD2, 0xE9). Clear the SCPS bit in the configuration SFR (CFG, 0xAF) and set the I2CEN bit in the I2C mode SFR (I2CMOD, 0xE8). Set the SCPS bit in the configuration SFR (CFG, 0xAF) and set the SPIEN bit in SPI Configuration SFR 2 (SPIMOD2, 0xE9). Set the ZX2 bit in the MODE3 energy measurement SFR (MODE3, 0x2B) Set the I2CEN bit in the I2C mode SFR (I2CMOD, 0xE8) or the SPIEN bit in SPI Configuration SFR 2 (SPIMOD2, 0xE9) to enable the I2C or SPI interface. Set the C/T0 bit in the Timer/Counter 0 and Timer/Counter 1 mode SFR (TMOD, 0x89) to enable T0 as an external event counter. Set the SS_EN bit in SPI Configuration SFR 1 (SPIMOD1, 0xE8). Set the SPIMS_b bit in SPI Configuration SFR 2 (SPIMOD2, 0xE9). Set the C/T1 bit in the Timer/Counter 0 and Timer/Counter 1 mode SFR (TMOD, 0x89) to enable T1 as an external event counter. Set the REN2 bit in the Serial Communications Control SFR (SCON2, 0xE1).
P0.6
Table 163. Port 1 Alternate Functions
Pin No. P1.0 Alternate Function RxD receiver data input for UART Rx Edge wake-up from PSM2 operating mode TxD transmitter data output for UART FP25 LCD segment pin Zero-Crossing Detection 1 FP24 LCD segment pin T2EX Timer 2 control input FP23 LCD segment pin T2 Timer 2 input FP22 LCD segment pin FP21 LCD segment pin FP20 LCD segment pin Alternate Function Enable Set the REN bit in the serial communications control register SFR (SCON, 0x98). Set RXPROG[1:0] = 11 in the peripheral configuration SFR (PERIPH, 0xF4). This pin becomes TxD as soon as data is written into SBUF. Set FP25EN in the LCD segment enable SFR (LCDSEGE, 0x97). Set the ZX1 bit in the MODE3 Energy Measurement SFR (MODE3, 0x2B) Set FP24EN in the LCD segment enable SFR (LCDSEGE, 0x97). Set EXEN2 in the Timer/Counter 2 control SFR (T2CON, 0xC8). Set FP23EN in the LCD segment enable SFR (LCDSEGE, 0x97). Set the C/T2 bit in the Timer/Counter 2 control SFR (T2CON, 0xC8) to enable T2 as an external event counter. Set FP22EN in the LCD segment enable SFR (LCDSEGE, 0x97). Set FP21EN in the LCD segment enable SFR (LCDSEGE, 0x97). Set FP20EN in the LCD segment enable SFR (LCDSEGE, 0x97).
P1.1 P1.2 P1.3 P1.4
P1.5 P1.6 P1.7
Table 164. Port 2 Alternate Functions
Pin No. P2.0 P2.1 P2.2 P2.3 Alternate Function FP18 LCD segment pin FP17 LCD segment pin FP16 LCD segment pin SDEN serial download pin sampled on reset. P2.3 is an output only. TxD2 transmitter data output for UART2. Alternate Function Enable Set FP18EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Set FP17EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Set FP16EN in the LCD Segment Enable 2 SFR (LCDSEGE2, 0xED). Enabled by default. This pin becomes TxD2 as soon as data is written into SBUF2.
Rev. PrB | Page 144 of 148
Preliminary Technical Data
PORT 0
Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, 0x80). The weak internal pull-ups for Port 0 are configured through the Port 0 weak pull-up enable SFR (PINMAP0, 0xB2); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP0.x. Port 0 pins also have various secondary functions as described in Table 162. The alternate functions of Port 0 pins can be activated only if the corresponding bit latch in the Port 0 SFR contains a 1. Otherwise, the port pin remains at 0.
ADE5166/ADE5169/ADE5566/ADE5569
Port 1 pins also have various secondary functions as described in Table 163. The alternate functions of Port 1 pins can be activated only if the corresponding bit latch in the Port 1 SFR contains a 1. Otherwise, the port pin remains at 0.
PORT 2
Port 2 is a 4-bit bidirectional port controlled directly through the bit-addressable Port 2 SFR (P2, 0xA0). Note that P2.3 can be used as an output only. Consequently, any read operation, such as a CPL P2.3, cannot be executed on this I/O. The weak internal pull-ups for Port 2 are configured through the Port 2 weak pull-up enable SFR (PINMAP2, 0xB4); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP2.x. Port 2 pins also have various secondary functions as described in Table 164. The alternate functions of Port 2 pins can be activated only if the corresponding bit latch in the Port 2 SFR contains a 1. Otherwise, the port pin remains at 0.
PORT 1
Port 1 is an 8-bit bidirectional port controlled directly through the bit-addressable Port 1 SFR (P1, 0x90). The weak internal pull-ups for Port 1 are configured through the Port 1 weak pullup enable SFR (PINMAP1, 0xB3); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP1.x.
Rev. PrB | Page 145 of 148
ADE5166/ADE5169/ADE5566/ADE5569
Each ADE5166/ADE5169/ADE5566/ADE5569 holds in its internal flash registers a value that defines its version. This value helps to determine if users have the latest version of the part.
Preliminary Technical Data
To access this value, the following procedure can be followed: 1. 2. 3. 4. 5. Launch HyperTerminal with a 9600 baud rate. Put the part in serial download mode by first holding SDEN to logic low then resetting the part. Hold the SDEN pin. Press and release the RESET pin. A string should appear on the HyperTerminal containing the part name an d version number.
DETERMINING THE VERSION OF THE ADE5166/ADE5169/ADE5566/ADE5569
Rev. PrB | Page 146 of 148
Preliminary Technical Data OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
1
ADE5166/ADE5169/ADE5566/ADE5569
12.20 12.00 SQ 11.80
64 49 48 PIN 1
TOP VIEW
(PINS DOWN)
10.20 10.00 SQ 9.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0
16 17 32
33
0.08 COPLANARITY
VIEW A
VIEW A
ROTATED 90 CCW
0.50 BSC LEAD PITCH
0.27 0.22 0.17
051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 97. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters
ORDERING GUIDE
Model1 ADE5169ASTZF622 ADE5169ASTZF62-RL2
1 2
Antitamper Yes Yes
di/dt Sensor Interface Yes Yes
VAR Yes Yes
Flash (kB) 62 62
Temperature Range -40C to +85C -40C to +85C
Package Description 64-Lead LQFP 64-Lead LQFP, Reel
Package Option ST-64-2 ST-64-2
All models have W + VA + rms, 5 V LCD, and RTC. Z = RoHS Compliant Part.
Rev. PrB | Page 147 of 148
ADE5166/ADE5169/ADE5566/ADE5569 NOTES
Preliminary Technical Data
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07411-0-4/08(PrB)
Rev. PrB | Page 148 of 148

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